Suspicious timing error prediction with in-cycle clock gating

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)

Abstract

Conventionally, circuits are designed to add pessimistic timing margin to solve delay variation problems, which guarantees 'always correct' operations. However, due to the fact that such a worst-case condition occurs rarely, the traditional pessimistic design method is therefore becoming one of the main obstacles for designers to achieve higher performance and/or ultra-low power consumption. By monitoring timing error occurrence during circuit operation, adaptive timing error detection and recovery methods have gained wide interests recently as a promising solution. As an extension of existing research, in this paper, we propose a suspicious timing error prediction method for performance or energy efficiency improvement in pipeline designs. Experimental results show that with when compared with typical margin designs, the proposed method can 1) achieve up to 1.41X throughput improvement with in-situ timing error prediction ability; and 2) allow the design to be overclocked by up to 1.88X with 'always correct' outputs.

Original languageEnglish
Title of host publicationProceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013
Pages335-340
Number of pages6
DOIs
Publication statusPublished - 2013 Jul 5
Event14th International Symposium on Quality Electronic Design, ISQED 2013 - Santa Clara, CA, United States
Duration: 2013 Mar 42013 Mar 6

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Conference

Conference14th International Symposium on Quality Electronic Design, ISQED 2013
CountryUnited States
CitySanta Clara, CA
Period13/3/413/3/6

Keywords

  • Timing error prediction
  • clock gating
  • robust design

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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  • Cite this

    Shi, Y., Igarashi, H., Togawa, N., & Yanagisawa, M. (2013). Suspicious timing error prediction with in-cycle clock gating. In Proceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013 (pp. 335-340). [6523631] (Proceedings - International Symposium on Quality Electronic Design, ISQED). https://doi.org/10.1109/ISQED.2013.6523631