Suspicious timing error prediction with in-cycle clock gating

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    14 Citations (Scopus)

    Abstract

    Conventionally, circuits are designed to add pessimistic timing margin to solve delay variation problems, which guarantees 'always correct' operations. However, due to the fact that such a worst-case condition occurs rarely, the traditional pessimistic design method is therefore becoming one of the main obstacles for designers to achieve higher performance and/or ultra-low power consumption. By monitoring timing error occurrence during circuit operation, adaptive timing error detection and recovery methods have gained wide interests recently as a promising solution. As an extension of existing research, in this paper, we propose a suspicious timing error prediction method for performance or energy efficiency improvement in pipeline designs. Experimental results show that with when compared with typical margin designs, the proposed method can 1) achieve up to 1.41X throughput improvement with in-situ timing error prediction ability; and 2) allow the design to be overclocked by up to 1.88X with 'always correct' outputs.

    Original languageEnglish
    Title of host publicationProceedings - International Symposium on Quality Electronic Design, ISQED
    Pages335-340
    Number of pages6
    DOIs
    Publication statusPublished - 2013
    Event14th International Symposium on Quality Electronic Design, ISQED 2013 - Santa Clara, CA
    Duration: 2013 Mar 42013 Mar 6

    Other

    Other14th International Symposium on Quality Electronic Design, ISQED 2013
    CitySanta Clara, CA
    Period13/3/413/3/6

    Fingerprint

    Clocks
    Networks (circuits)
    Error detection
    Energy efficiency
    Electric power utilization
    Pipelines
    Throughput
    Monitoring

    Keywords

    • clock gating
    • robust design
    • Timing error prediction

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering
    • Safety, Risk, Reliability and Quality

    Cite this

    Shi, Y., Igarashi, H., Togawa, N., & Yanagisawa, M. (2013). Suspicious timing error prediction with in-cycle clock gating. In Proceedings - International Symposium on Quality Electronic Design, ISQED (pp. 335-340). [6523631] https://doi.org/10.1109/ISQED.2013.6523631

    Suspicious timing error prediction with in-cycle clock gating. / Shi, Youhua; Igarashi, Hiroaki; Togawa, Nozomu; Yanagisawa, Masao.

    Proceedings - International Symposium on Quality Electronic Design, ISQED. 2013. p. 335-340 6523631.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Shi, Y, Igarashi, H, Togawa, N & Yanagisawa, M 2013, Suspicious timing error prediction with in-cycle clock gating. in Proceedings - International Symposium on Quality Electronic Design, ISQED., 6523631, pp. 335-340, 14th International Symposium on Quality Electronic Design, ISQED 2013, Santa Clara, CA, 13/3/4. https://doi.org/10.1109/ISQED.2013.6523631
    Shi Y, Igarashi H, Togawa N, Yanagisawa M. Suspicious timing error prediction with in-cycle clock gating. In Proceedings - International Symposium on Quality Electronic Design, ISQED. 2013. p. 335-340. 6523631 https://doi.org/10.1109/ISQED.2013.6523631
    Shi, Youhua ; Igarashi, Hiroaki ; Togawa, Nozomu ; Yanagisawa, Masao. / Suspicious timing error prediction with in-cycle clock gating. Proceedings - International Symposium on Quality Electronic Design, ISQED. 2013. pp. 335-340
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