Symmetry constraint based on mismatch analysis for analog layout in SOI technology

Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    14 Citations (Scopus)

    Abstract

    The conventional tools for mismatch elimination such as geometric symmetry and common centroid technology can only eliminate systematic mismatch, but can do little to reduce random mismatch and thermal-induced mismatch. As the development of VLSI technology, the random mismatch is becoming more and more serious. And in the context of Silicon on Insulator (SOI), the self-heating effect leads to unbearable thermal-induced mismatch. Therefore, in this paper, we first propose a new model which can estimate the combination effect of both random mismatch and thermal-induced mismatch by mismatch analysis and SPICE simulation. And in order to meet the different sensitivities of different symmetry pairs, an automatic classification tool and a configurable optimization process are also introduced. All of these are embedded in the floorplanning process. The final experimental results prove the effectiveness of our method.

    Original languageEnglish
    Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
    Pages772-775
    Number of pages4
    DOIs
    Publication statusPublished - 2008
    Event2008 Asia and South Pacific Design Automation Conference, ASP-DAC - Seoul
    Duration: 2008 Mar 212008 Mar 24

    Other

    Other2008 Asia and South Pacific Design Automation Conference, ASP-DAC
    CitySeoul
    Period08/3/2108/3/24

    Fingerprint

    Silicon on insulator technology
    SPICE
    Heating
    Silicon
    Hot Temperature

    ASJC Scopus subject areas

    • Engineering(all)

    Cite this

    Liu, J., Dong, S., Hong, X., Wang, Y., He, O., & Goto, S. (2008). Symmetry constraint based on mismatch analysis for analog layout in SOI technology. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 772-775). [4484055] https://doi.org/10.1109/ASPDAC.2008.4484055

    Symmetry constraint based on mismatch analysis for analog layout in SOI technology. / Liu, Jiayi; Dong, Sheqin; Hong, Xianlong; Wang, Yibo; He, Ou; Goto, Satoshi.

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2008. p. 772-775 4484055.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Liu, J, Dong, S, Hong, X, Wang, Y, He, O & Goto, S 2008, Symmetry constraint based on mismatch analysis for analog layout in SOI technology. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC., 4484055, pp. 772-775, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC, Seoul, 08/3/21. https://doi.org/10.1109/ASPDAC.2008.4484055
    Liu J, Dong S, Hong X, Wang Y, He O, Goto S. Symmetry constraint based on mismatch analysis for analog layout in SOI technology. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2008. p. 772-775. 4484055 https://doi.org/10.1109/ASPDAC.2008.4484055
    Liu, Jiayi ; Dong, Sheqin ; Hong, Xianlong ; Wang, Yibo ; He, Ou ; Goto, Satoshi. / Symmetry constraint based on mismatch analysis for analog layout in SOI technology. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. 2008. pp. 772-775
    @inproceedings{88f87939a0994979a18f8e7919de9c54,
    title = "Symmetry constraint based on mismatch analysis for analog layout in SOI technology",
    abstract = "The conventional tools for mismatch elimination such as geometric symmetry and common centroid technology can only eliminate systematic mismatch, but can do little to reduce random mismatch and thermal-induced mismatch. As the development of VLSI technology, the random mismatch is becoming more and more serious. And in the context of Silicon on Insulator (SOI), the self-heating effect leads to unbearable thermal-induced mismatch. Therefore, in this paper, we first propose a new model which can estimate the combination effect of both random mismatch and thermal-induced mismatch by mismatch analysis and SPICE simulation. And in order to meet the different sensitivities of different symmetry pairs, an automatic classification tool and a configurable optimization process are also introduced. All of these are embedded in the floorplanning process. The final experimental results prove the effectiveness of our method.",
    author = "Jiayi Liu and Sheqin Dong and Xianlong Hong and Yibo Wang and Ou He and Satoshi Goto",
    year = "2008",
    doi = "10.1109/ASPDAC.2008.4484055",
    language = "English",
    isbn = "9781424419227",
    pages = "772--775",
    booktitle = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

    }

    TY - GEN

    T1 - Symmetry constraint based on mismatch analysis for analog layout in SOI technology

    AU - Liu, Jiayi

    AU - Dong, Sheqin

    AU - Hong, Xianlong

    AU - Wang, Yibo

    AU - He, Ou

    AU - Goto, Satoshi

    PY - 2008

    Y1 - 2008

    N2 - The conventional tools for mismatch elimination such as geometric symmetry and common centroid technology can only eliminate systematic mismatch, but can do little to reduce random mismatch and thermal-induced mismatch. As the development of VLSI technology, the random mismatch is becoming more and more serious. And in the context of Silicon on Insulator (SOI), the self-heating effect leads to unbearable thermal-induced mismatch. Therefore, in this paper, we first propose a new model which can estimate the combination effect of both random mismatch and thermal-induced mismatch by mismatch analysis and SPICE simulation. And in order to meet the different sensitivities of different symmetry pairs, an automatic classification tool and a configurable optimization process are also introduced. All of these are embedded in the floorplanning process. The final experimental results prove the effectiveness of our method.

    AB - The conventional tools for mismatch elimination such as geometric symmetry and common centroid technology can only eliminate systematic mismatch, but can do little to reduce random mismatch and thermal-induced mismatch. As the development of VLSI technology, the random mismatch is becoming more and more serious. And in the context of Silicon on Insulator (SOI), the self-heating effect leads to unbearable thermal-induced mismatch. Therefore, in this paper, we first propose a new model which can estimate the combination effect of both random mismatch and thermal-induced mismatch by mismatch analysis and SPICE simulation. And in order to meet the different sensitivities of different symmetry pairs, an automatic classification tool and a configurable optimization process are also introduced. All of these are embedded in the floorplanning process. The final experimental results prove the effectiveness of our method.

    UR - http://www.scopus.com/inward/record.url?scp=49549085687&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=49549085687&partnerID=8YFLogxK

    U2 - 10.1109/ASPDAC.2008.4484055

    DO - 10.1109/ASPDAC.2008.4484055

    M3 - Conference contribution

    SN - 9781424419227

    SP - 772

    EP - 775

    BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

    ER -