System architecture of parallel processing system - Harray

Hayato Yamana, Toshikazu Marushima, Takashi Hagiwara, Yoichi Muraoka

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)

    Abstract

    This paper proposes a parallel processing system - Harray-for scientific computations. Data flow computers are expected to obtain the high performance because they can extract parallelism fully from a program. However, they have many problems, such as the difficulty of controlling the sequence of execution. The - Harray - system is an array processor which adapts two levels of control mechanism; data flow execution in each processor and control flow between processors, in order to take full advantage of both mechanisms. A task which is assigned to a processor is called a "macro-block". Three types of macro-blocking and three types of activation schemes for the macro-block which initiates its execution are introduced in order to attain the high performance. Moreover, a hardware synchronization mechanism is used to reduce synchronization overhead and to gain the liner speedup of the - Harray - system. In this paper, the system architecture of the - Harray - system and its performance evaluation by software simulation are presented.

    Original languageEnglish
    Title of host publicationProceedings of the 2nd International Conference on Supercomputing, ICS 1988
    PublisherAssociation for Computing Machinery
    Pages76-89
    Number of pages14
    VolumePart F130184
    ISBN (Electronic)0897912721
    DOIs
    Publication statusPublished - 1988 Jun 1
    Event2nd International Conference on Supercomputing, ICS 1988 - St. Malo, France
    Duration: 1988 Jul 41988 Jul 8

    Other

    Other2nd International Conference on Supercomputing, ICS 1988
    CountryFrance
    CitySt. Malo
    Period88/7/488/7/8

    ASJC Scopus subject areas

    • Computer Science(all)

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  • Cite this

    Yamana, H., Marushima, T., Hagiwara, T., & Muraoka, Y. (1988). System architecture of parallel processing system - Harray. In Proceedings of the 2nd International Conference on Supercomputing, ICS 1988 (Vol. Part F130184, pp. 76-89). Association for Computing Machinery. https://doi.org/10.1145/55364.55372