Technology roadmap on SOC testing issues on SOC testing in DSM Era

Takashi Aikyo

Research output: Contribution to conferencePaperpeer-review

Abstract

Deep sub-micro technology is rapidly leading to exceedingly complex, billion-transistor chips. By these technology evolutions, a system is integrated into a chip so called a system-on-a-chip (SOC). In order to bridge the productivity gap between available transistors and able to be designed in SOC, higher-level behavioral language and design re-use become more common. However, these techniques affect test methodologies and failure analysis of SOC. On the other hand, SOCs are implementation as a collection of heterogeneous circuits such like ASICs, DRAMs and analog circuits, so it will be large impact for Design for Testability techniques (DFT) and test cost issues. To solve the complex testing issues that are arising with SOCs, we show technology requirements about following seven areas.

Original languageEnglish
Pages38
Number of pages1
Publication statusPublished - 2001
Externally publishedYes
Event4th International Conference on ASIC Proceedings - Shanghai, China
Duration: 2001 Oct 232001 Oct 25

Conference

Conference4th International Conference on ASIC Proceedings
Country/TerritoryChina
CityShanghai
Period01/10/2301/10/25

ASJC Scopus subject areas

  • Engineering(all)

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