Temperature compensated piezoresistor fabricated by high energy ion implantation

Takahiro Nishimoto, Shuichi Shoji, Kazuyuki Minami, Masayoshi Esashi

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

We developed piezoresistors with an intrinsic compensation of the offset temperature characteristics. High energy ion implantation was applied to fabricate this type of piezoresistor [1]. The dopant profile of the buried piezoresistor resembles to that of the junction gate field effect transistor (JFET). The buried layer corresponds to a channel of JFET, and the substrate bias corresponds to the gate voltage. Owing to the independent temperature varying parameters, i.e., width of the depletion layer and carrier mobility in the channel, the drain current of the JFET has a temperature independent point at an appropriate gate source voltage. The effect was used in the new type of buried piezoresistor which has a driving point of zero temperature coefficient of resistance at an appropriate gate source voltage.

Original languageEnglish
Pages (from-to)152-156
Number of pages5
JournalIEICE Transactions on Electronics
VolumeE78-C
Issue number2
Publication statusPublished - 1995 Feb
Externally publishedYes

Fingerprint

Junction gate field effect transistors
Ion implantation
Electric potential
Temperature
Drain current
Carrier mobility
Doping (additives)
Substrates

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Temperature compensated piezoresistor fabricated by high energy ion implantation. / Nishimoto, Takahiro; Shoji, Shuichi; Minami, Kazuyuki; Esashi, Masayoshi.

In: IEICE Transactions on Electronics, Vol. E78-C, No. 2, 02.1995, p. 152-156.

Research output: Contribution to journalArticle

Nishimoto, Takahiro ; Shoji, Shuichi ; Minami, Kazuyuki ; Esashi, Masayoshi. / Temperature compensated piezoresistor fabricated by high energy ion implantation. In: IEICE Transactions on Electronics. 1995 ; Vol. E78-C, No. 2. pp. 152-156.
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