Test data compression for scan-based BIST aiming at 100x compression rate

Masayuki Arai*, Satoshi Fukumoto, Kazuhiko Iwasaki, Tatsuru Matsuo, Takahisa Hiraide, Hideaki Konishi, Michiaki Emori, Takashi Aikyo

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


We developed test data compression scheme for scanbased BIST, aiming to compress test stimuli and responses by more than 100 times. As scan-BIST architecture, we adopt BIST-Aided Scan Test (BAST), and combines four techniques: the invert-and-shift operation, runlength compression, scan address partitioning, and LFSR pre-shifting. Our scheme achieved a 100x compression rate in environments where Xs do not occur without reducing the fault coverage of the original ATPG vectors. Furthermore, we enhanced the masking logic to reduce data for X-masking so that test data is still compressed to 1/100 in a practical environment where Xs occur. We applied our scheme to five real VLSI chips, and the technique compressed the test data by 100x for scan-based BIST.

Original languageEnglish
Pages (from-to)726-735
Number of pages10
JournalIEICE Transactions on Information and Systems
Issue number3
Publication statusPublished - 2008 Mar
Externally publishedYes


  • ATPG
  • BIST-aided scan test
  • Test data compression
  • Test response compaction
  • X-value

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence


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