Test data compression of 100x for scan-based BIST

Masayuki Arai; Satoshi Fukumoto; Kazuhiko Iwasaki; Tatsuru Matsuo; Takahisa Hiraide; Hideaki Konishi; Michiaki Emori; Takashi Aikyo

doi:10.1109/TEST.2006.297664

Test data compression of 100x for scan-based BIST

Masayuki Arai^*, Satoshi Fukumoto, Kazuhiko Iwasaki, Tatsuru Matsuo, Takahisa Hiraide, Hideaki Konishi, Michiaki Emori, Takashi Aikyo

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

Abstract

We developed a scheme for scan-based BIST that can compress test stimuli and responses by more than 100 times. The scheme is based on a scan-BIST architecture, and combines four techniques: the invert-and-shift operation, run-length compression, scan address partitioning, and LFSR pre-shifting. Our scheme achieved a 10Ox compression rate in environments where Xs do not occur without reducing the fault coverage of the original ATPG vectors. Furthermore, we enhanced the masking logic to reduce data for X-masking so that test data is still compressed to 1/100 in a practical environment where Xs occur. We applied our scheme to five real VLSI chips, and the technique compressed the test data by 100x for scan-based BIST.

Original language	English
Title of host publication	2006 IEEE International Test Conference, ITC
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	1424402921, 9781424402922
DOIs	https://doi.org/10.1109/TEST.2006.297664
Publication status	Published - 2006
Externally published	Yes
Event	2006 IEEE International Test Conference, ITC - Santa Clara, CA, United States Duration: 2006 Oct 22 → 2006 Oct 27

Publication series

Name	Proceedings - International Test Conference
ISSN (Print)	1089-3539

Conference

Conference	2006 IEEE International Test Conference, ITC
Country/Territory	United States
City	Santa Clara, CA
Period	06/10/22 → 06/10/27

ASJC Scopus subject areas

Electrical and Electronic Engineering
Applied Mathematics

Access to Document

10.1109/TEST.2006.297664

Cite this

Arai, M, Fukumoto, S, Iwasaki, K, Matsuo, T, Hiraide, T, Konishi, H, Emori, M & Aikyo, T 2006, Test data compression of 100x for scan-based BIST. in 2006 IEEE International Test Conference, ITC., 4079342, Proceedings - International Test Conference, Institute of Electrical and Electronics Engineers Inc., 2006 IEEE International Test Conference, ITC, Santa Clara, CA, United States, 06/10/22. https://doi.org/10.1109/TEST.2006.297664

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title = "Test data compression of 100x for scan-based BIST",

abstract = "We developed a scheme for scan-based BIST that can compress test stimuli and responses by more than 100 times. The scheme is based on a scan-BIST architecture, and combines four techniques: the invert-and-shift operation, run-length compression, scan address partitioning, and LFSR pre-shifting. Our scheme achieved a 10Ox compression rate in environments where Xs do not occur without reducing the fault coverage of the original ATPG vectors. Furthermore, we enhanced the masking logic to reduce data for X-masking so that test data is still compressed to 1/100 in a practical environment where Xs occur. We applied our scheme to five real VLSI chips, and the technique compressed the test data by 100x for scan-based BIST.",

author = "Masayuki Arai and Satoshi Fukumoto and Kazuhiko Iwasaki and Tatsuru Matsuo and Takahisa Hiraide and Hideaki Konishi and Michiaki Emori and Takashi Aikyo",

year = "2006",

doi = "10.1109/TEST.2006.297664",

language = "English",

isbn = "1424402921",

series = "Proceedings - International Test Conference",

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note = "2006 IEEE International Test Conference, ITC ; Conference date: 22-10-2006 Through 27-10-2006",

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T1 - Test data compression of 100x for scan-based BIST

AU - Arai, Masayuki

AU - Fukumoto, Satoshi

AU - Iwasaki, Kazuhiko

AU - Matsuo, Tatsuru

AU - Hiraide, Takahisa

AU - Konishi, Hideaki

AU - Emori, Michiaki

AU - Aikyo, Takashi

PY - 2006

Y1 - 2006

N2 - We developed a scheme for scan-based BIST that can compress test stimuli and responses by more than 100 times. The scheme is based on a scan-BIST architecture, and combines four techniques: the invert-and-shift operation, run-length compression, scan address partitioning, and LFSR pre-shifting. Our scheme achieved a 10Ox compression rate in environments where Xs do not occur without reducing the fault coverage of the original ATPG vectors. Furthermore, we enhanced the masking logic to reduce data for X-masking so that test data is still compressed to 1/100 in a practical environment where Xs occur. We applied our scheme to five real VLSI chips, and the technique compressed the test data by 100x for scan-based BIST.

AB - We developed a scheme for scan-based BIST that can compress test stimuli and responses by more than 100 times. The scheme is based on a scan-BIST architecture, and combines four techniques: the invert-and-shift operation, run-length compression, scan address partitioning, and LFSR pre-shifting. Our scheme achieved a 10Ox compression rate in environments where Xs do not occur without reducing the fault coverage of the original ATPG vectors. Furthermore, we enhanced the masking logic to reduce data for X-masking so that test data is still compressed to 1/100 in a practical environment where Xs occur. We applied our scheme to five real VLSI chips, and the technique compressed the test data by 100x for scan-based BIST.

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M3 - Conference contribution

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SN - 9781424402922

T3 - Proceedings - International Test Conference

BT - 2006 IEEE International Test Conference, ITC

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2006 IEEE International Test Conference, ITC

Y2 - 22 October 2006 through 27 October 2006

ER -

Test data compression of 100x for scan-based BIST

Abstract

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Conference

ASJC Scopus subject areas

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