Test data compression of 100x for scan-based BIST

Masayuki Arai*, Satoshi Fukumoto, Kazuhiko Iwasaki, Tatsuru Matsuo, Takahisa Hiraide, Hideaki Konishi, Michiaki Emori, Takashi Aikyo

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)


We developed a scheme for scan-based BIST that can compress test stimuli and responses by more than 100 times. The scheme is based on a scan-BIST architecture, and combines four techniques: the invert-and-shift operation, run-length compression, scan address partitioning, and LFSR pre-shifting. Our scheme achieved a 10Ox compression rate in environments where Xs do not occur without reducing the fault coverage of the original ATPG vectors. Furthermore, we enhanced the masking logic to reduce data for X-masking so that test data is still compressed to 1/100 in a practical environment where Xs occur. We applied our scheme to five real VLSI chips, and the technique compressed the test data by 100x for scan-based BIST.

Original languageEnglish
Title of host publication2006 IEEE International Test Conference, ITC
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)1424402921, 9781424402922
Publication statusPublished - 2006
Externally publishedYes
Event2006 IEEE International Test Conference, ITC - Santa Clara, CA, United States
Duration: 2006 Oct 222006 Oct 27

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539


Conference2006 IEEE International Test Conference, ITC
Country/TerritoryUnited States
CitySanta Clara, CA

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Applied Mathematics


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