Test synthesis approach to reducing BALLAST DFT overhead

Douglas Chang*, Mike Tien Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang Ting Cheng

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review


In this paper, we present a test synthesis approach which integrates BALLAST (BALAnced structure Scan Test) with an enhanced test point insertion (TPI) algorithm to functionally scan the flip-flops chosen by BALLAST. BALLAST is an attractive partial scan technique in that it offers combinational ATPG efficiency while promising to reduce full scan overhead. However, the practical problem with BALLAST is it typically requires more scan flip-flops than other partial scan techniques. The TPI enhancements enable TPI to aim at the reduction of BALLAST overhead. The enhancements include a more flexible test point insertion heuristic, a modified gain function which enables TPI to target a selected set of flip-flops, and a more efficient procedure to remove redundant test points. The experimental results on nine benchmark circuits show the proposed test synthesis approach can achieve on average 38% area saving compared to full scan, while BALLAST alone achieves 17%.

Original languageEnglish
Pages (from-to)466-471
Number of pages6
JournalProceedings - Design Automation Conference
Publication statusPublished - 1997
Externally publishedYes
EventProceedings of the 1997 34th Design Automation Conference - Anaheim, CA, USA
Duration: 1997 Jun 91997 Jun 13

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering


Dive into the research topics of 'Test synthesis approach to reducing BALLAST DFT overhead'. Together they form a unique fingerprint.

Cite this