The impact of RTN on performance fluctuation in CMOS logic circuits

Kyosuke Ito*, Takashi Matsumoto, Shinichi Nishizawa, Hiroki Sunagawa, Kazutoshi Kobayashi, Hidetoshi Onodera

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

24 Citations (Scopus)

Abstract

In this paper, the impact of Random Telegraph Noise (RTN) on CMOS logic circuits observed in a Circuit Matrix Array is reported. We discuss the behavior of RTN under circuit operation, and reveal that the impact of RTN, which is much smaller than that of within-die variation in a 65nm process, can have a severe effect on the performance of a sequential logic gate under low voltage operation.

Original languageEnglish
Title of host publication2011 International Reliability Physics Symposium, IRPS 2011
PagesCR.5.1-CR.5.4
DOIs
Publication statusPublished - 2011
Externally publishedYes
Event49th International Reliability Physics Symposium, IRPS 2011 - Monterey, CA, United States
Duration: 2011 Apr 102011 Apr 14

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026

Conference

Conference49th International Reliability Physics Symposium, IRPS 2011
Country/TerritoryUnited States
CityMonterey, CA
Period11/4/1011/4/14

ASJC Scopus subject areas

  • Engineering(all)

Fingerprint

Dive into the research topics of 'The impact of RTN on performance fluctuation in CMOS logic circuits'. Together they form a unique fingerprint.

Cite this