The impact of RTN on performance fluctuation in CMOS logic circuits

Kyosuke Ito; Takashi Matsumoto; Shinichi Nishizawa; Hiroki Sunagawa; Kazutoshi Kobayashi; Hidetoshi Onodera

doi:10.1109/IRPS.2011.5784563

The impact of RTN on performance fluctuation in CMOS logic circuits

Kyosuke Ito^*, Takashi Matsumoto, Shinichi Nishizawa, Hiroki Sunagawa, Kazutoshi Kobayashi, Hidetoshi Onodera

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

24 Citations (Scopus)

Abstract

In this paper, the impact of Random Telegraph Noise (RTN) on CMOS logic circuits observed in a Circuit Matrix Array is reported. We discuss the behavior of RTN under circuit operation, and reveal that the impact of RTN, which is much smaller than that of within-die variation in a 65nm process, can have a severe effect on the performance of a sequential logic gate under low voltage operation.

Original language	English
Title of host publication	2011 International Reliability Physics Symposium, IRPS 2011
Pages	CR.5.1-CR.5.4
DOIs	https://doi.org/10.1109/IRPS.2011.5784563
Publication status	Published - 2011
Externally published	Yes
Event	49th International Reliability Physics Symposium, IRPS 2011 - Monterey, CA, United States Duration: 2011 Apr 10 → 2011 Apr 14

Publication series

Name	IEEE International Reliability Physics Symposium Proceedings
ISSN (Print)	1541-7026

Conference

Conference	49th International Reliability Physics Symposium, IRPS 2011
Country/Territory	United States
City	Monterey, CA
Period	11/4/10 → 11/4/14

ASJC Scopus subject areas

Engineering(all)

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10.1109/IRPS.2011.5784563

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The impact of RTN on performance fluctuation in CMOS logic circuits. / Ito, Kyosuke; Matsumoto, Takashi; Nishizawa, Shinichi et al.

2011 International Reliability Physics Symposium, IRPS 2011. 2011. p. CR.5.1-CR.5.4 5784563 (IEEE International Reliability Physics Symposium Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ito, K, Matsumoto, T, Nishizawa, S, Sunagawa, H, Kobayashi, K & Onodera, H 2011, The impact of RTN on performance fluctuation in CMOS logic circuits. in 2011 International Reliability Physics Symposium, IRPS 2011., 5784563, IEEE International Reliability Physics Symposium Proceedings, pp. CR.5.1-CR.5.4, 49th International Reliability Physics Symposium, IRPS 2011, Monterey, CA, United States, 11/4/10. https://doi.org/10.1109/IRPS.2011.5784563

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AU - Onodera, Hidetoshi

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The impact of RTN on performance fluctuation in CMOS logic circuits

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