Abstract
3D gated clock tree synthesis (CTS) mainly consists of three steps: 1) abstract clock topology generation; 2) layer embedding for minimal TSV allocation and 3) clock tree routing with gate and buffer insertion. In this paper, a self-tuning spectral clustering based nearest-neighbor selection (SSC-NNS) algorithm with parallel structure is proposed to achieve high time efficiency in clock tree topology generation, with reduced runtime. In addition, a postorder traversal based layer embedding (PTLE) strategy is adopted for determining the embedding layer of internal nodes with minimal TSVges. Experimental results show that the proposed method achieves 32% and 82% runtime reduction on ISPD2009 and IBM benchmarks respectively compared with the state-of-the-art 3D work. Besides, the TSV count is also reduced by 46% on ISPD2009 benchmarks.
| Original language | English |
|---|---|
| Title of host publication | 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 1200-1203 |
| Number of pages | 4 |
| Volume | 2017-August |
| ISBN (Electronic) | 9781509063895 |
| DOIs | |
| Publication status | Published - 2017 Sep 27 |
| Event | 60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017 - Boston, United States Duration: 2017 Aug 6 → 2017 Aug 9 |
Other
| Other | 60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017 |
|---|---|
| Country | United States |
| City | Boston |
| Period | 17/8/6 → 17/8/9 |
Fingerprint
Keywords
- 3D clock tree synthesis
- Parallel
- Self-tuning
- Spectral clustering
- TSV
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
Cite this
Time-efficient and TSV-aware 3D gated clock tree synthesis based on self-tuning spectral clustering. / Yang, Fan; Lin, Minghao; Sun, Heming; Kimura, Shinji.
2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017. Vol. 2017-August Institute of Electrical and Electronics Engineers Inc., 2017. p. 1200-1203 8053144.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Time-efficient and TSV-aware 3D gated clock tree synthesis based on self-tuning spectral clustering
AU - Yang, Fan
AU - Lin, Minghao
AU - Sun, Heming
AU - Kimura, Shinji
PY - 2017/9/27
Y1 - 2017/9/27
N2 - 3D gated clock tree synthesis (CTS) mainly consists of three steps: 1) abstract clock topology generation; 2) layer embedding for minimal TSV allocation and 3) clock tree routing with gate and buffer insertion. In this paper, a self-tuning spectral clustering based nearest-neighbor selection (SSC-NNS) algorithm with parallel structure is proposed to achieve high time efficiency in clock tree topology generation, with reduced runtime. In addition, a postorder traversal based layer embedding (PTLE) strategy is adopted for determining the embedding layer of internal nodes with minimal TSVges. Experimental results show that the proposed method achieves 32% and 82% runtime reduction on ISPD2009 and IBM benchmarks respectively compared with the state-of-the-art 3D work. Besides, the TSV count is also reduced by 46% on ISPD2009 benchmarks.
AB - 3D gated clock tree synthesis (CTS) mainly consists of three steps: 1) abstract clock topology generation; 2) layer embedding for minimal TSV allocation and 3) clock tree routing with gate and buffer insertion. In this paper, a self-tuning spectral clustering based nearest-neighbor selection (SSC-NNS) algorithm with parallel structure is proposed to achieve high time efficiency in clock tree topology generation, with reduced runtime. In addition, a postorder traversal based layer embedding (PTLE) strategy is adopted for determining the embedding layer of internal nodes with minimal TSVges. Experimental results show that the proposed method achieves 32% and 82% runtime reduction on ISPD2009 and IBM benchmarks respectively compared with the state-of-the-art 3D work. Besides, the TSV count is also reduced by 46% on ISPD2009 benchmarks.
KW - 3D clock tree synthesis
KW - Parallel
KW - Self-tuning
KW - Spectral clustering
KW - TSV
UR - http://www.scopus.com/inward/record.url?scp=85034040193&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85034040193&partnerID=8YFLogxK
U2 - 10.1109/MWSCAS.2017.8053144
DO - 10.1109/MWSCAS.2017.8053144
M3 - Conference contribution
VL - 2017-August
SP - 1200
EP - 1203
BT - 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017
PB - Institute of Electrical and Electronics Engineers Inc.
ER -