Time-efficient and TSV-aware 3D gated clock tree synthesis based on self-tuning spectral clustering

Fan Yang, Minghao Lin, Heming Sun, Shinji Kimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

3D gated clock tree synthesis (CTS) mainly consists of three steps: 1) abstract clock topology generation; 2) layer embedding for minimal TSV allocation and 3) clock tree routing with gate and buffer insertion. In this paper, a self-tuning spectral clustering based nearest-neighbor selection (SSC-NNS) algorithm with parallel structure is proposed to achieve high time efficiency in clock tree topology generation, with reduced runtime. In addition, a postorder traversal based layer embedding (PTLE) strategy is adopted for determining the embedding layer of internal nodes with minimal TSVges. Experimental results show that the proposed method achieves 32% and 82% runtime reduction on ISPD2009 and IBM benchmarks respectively compared with the state-of-the-art 3D work. Besides, the TSV count is also reduced by 46% on ISPD2009 benchmarks.

Original languageEnglish
Title of host publication2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1200-1203
Number of pages4
Volume2017-August
ISBN (Electronic)9781509063895
DOIs
Publication statusPublished - 2017 Sep 27
Event60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017 - Boston, United States
Duration: 2017 Aug 62017 Aug 9

Other

Other60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017
CountryUnited States
CityBoston
Period17/8/617/8/9

Fingerprint

Clocks
Tuning
Topology
Buffers

Keywords

  • 3D clock tree synthesis
  • Parallel
  • Self-tuning
  • Spectral clustering
  • TSV

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Yang, F., Lin, M., Sun, H., & Kimura, S. (2017). Time-efficient and TSV-aware 3D gated clock tree synthesis based on self-tuning spectral clustering. In 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017 (Vol. 2017-August, pp. 1200-1203). [8053144] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MWSCAS.2017.8053144

Time-efficient and TSV-aware 3D gated clock tree synthesis based on self-tuning spectral clustering. / Yang, Fan; Lin, Minghao; Sun, Heming; Kimura, Shinji.

2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017. Vol. 2017-August Institute of Electrical and Electronics Engineers Inc., 2017. p. 1200-1203 8053144.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yang, F, Lin, M, Sun, H & Kimura, S 2017, Time-efficient and TSV-aware 3D gated clock tree synthesis based on self-tuning spectral clustering. in 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017. vol. 2017-August, 8053144, Institute of Electrical and Electronics Engineers Inc., pp. 1200-1203, 60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, United States, 17/8/6. https://doi.org/10.1109/MWSCAS.2017.8053144
Yang F, Lin M, Sun H, Kimura S. Time-efficient and TSV-aware 3D gated clock tree synthesis based on self-tuning spectral clustering. In 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017. Vol. 2017-August. Institute of Electrical and Electronics Engineers Inc. 2017. p. 1200-1203. 8053144 https://doi.org/10.1109/MWSCAS.2017.8053144
Yang, Fan ; Lin, Minghao ; Sun, Heming ; Kimura, Shinji. / Time-efficient and TSV-aware 3D gated clock tree synthesis based on self-tuning spectral clustering. 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017. Vol. 2017-August Institute of Electrical and Electronics Engineers Inc., 2017. pp. 1200-1203
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