Abstract
3D gated clock tree synthesis (CTS) mainly consists of three steps: 1) abstract clock topology generation; 2) layer embedding for minimal TSV allocation and 3) clock tree routing with gate and buffer insertion. In this paper, a self-tuning spectral clustering based nearest-neighbor selection (SSC-NNS) algorithm with parallel structure is proposed to achieve high time efficiency in clock tree topology generation, with reduced runtime. In addition, a postorder traversal based layer embedding (PTLE) strategy is adopted for determining the embedding layer of internal nodes with minimal TSVges. Experimental results show that the proposed method achieves 32% and 82% runtime reduction on ISPD2009 and IBM benchmarks respectively compared with the state-of-the-art 3D work. Besides, the TSV count is also reduced by 46% on ISPD2009 benchmarks.
Original language | English |
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Title of host publication | 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 1200-1203 |
Number of pages | 4 |
Volume | 2017-August |
ISBN (Electronic) | 9781509063895 |
DOIs | |
Publication status | Published - 2017 Sep 27 |
Event | 60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017 - Boston, United States Duration: 2017 Aug 6 → 2017 Aug 9 |
Other
Other | 60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017 |
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Country/Territory | United States |
City | Boston |
Period | 17/8/6 → 17/8/9 |
Keywords
- 3D clock tree synthesis
- Parallel
- Self-tuning
- Spectral clustering
- TSV
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering