Timing and resource constrained leakage power aware scheduling in high-level synthesis

Nan Wang, Cong Hao, Nan Liu, Haoran Zhang, Takeshi Yoshimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we address the problem of scheduling operations into proper control steps with dual threshold voltage techniques under timing and resource constraints. Our work first remove operations' mobility overlaps to eliminate the data dependencies, and a simulated-annealing based method then explores the optimal mobility overlap removal. For each mobility overlap removal solution, operations are initialized with a proper threshold voltage (Vth), and then scheduled averagely at each control step, which usually violates the resource constraints. A weighted interval scheduling model is built, and the set of maximum weighted operations whose mobilities do not share the same control step are selected and reassigned with low-Vth, until the resource constraints are met. The reassigned operations need to be rescheduled since their threshold voltages are changed. This procedure is repeated until all the operations are scheduled and resource constraints are satisfied. Experimental results show the proposed algorithm's effectiveness.

Original languageEnglish
Title of host publicationProceedings of International Conference on ASIC
PublisherIEEE Computer Society
ISBN (Print)9781467364157
DOIs
Publication statusPublished - 2013
Event2013 IEEE 10th International Conference on ASIC, ASICON 2013 - Shenzhen
Duration: 2013 Oct 282013 Oct 31

Other

Other2013 IEEE 10th International Conference on ASIC, ASICON 2013
CityShenzhen
Period13/10/2813/10/31

Fingerprint

Threshold voltage
Scheduling
Simulated annealing
High level synthesis

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Wang, N., Hao, C., Liu, N., Zhang, H., & Yoshimura, T. (2013). Timing and resource constrained leakage power aware scheduling in high-level synthesis. In Proceedings of International Conference on ASIC [6811939] IEEE Computer Society. https://doi.org/10.1109/ASICON.2013.6811939

Timing and resource constrained leakage power aware scheduling in high-level synthesis. / Wang, Nan; Hao, Cong; Liu, Nan; Zhang, Haoran; Yoshimura, Takeshi.

Proceedings of International Conference on ASIC. IEEE Computer Society, 2013. 6811939.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wang, N, Hao, C, Liu, N, Zhang, H & Yoshimura, T 2013, Timing and resource constrained leakage power aware scheduling in high-level synthesis. in Proceedings of International Conference on ASIC., 6811939, IEEE Computer Society, 2013 IEEE 10th International Conference on ASIC, ASICON 2013, Shenzhen, 13/10/28. https://doi.org/10.1109/ASICON.2013.6811939
Wang N, Hao C, Liu N, Zhang H, Yoshimura T. Timing and resource constrained leakage power aware scheduling in high-level synthesis. In Proceedings of International Conference on ASIC. IEEE Computer Society. 2013. 6811939 https://doi.org/10.1109/ASICON.2013.6811939
Wang, Nan ; Hao, Cong ; Liu, Nan ; Zhang, Haoran ; Yoshimura, Takeshi. / Timing and resource constrained leakage power aware scheduling in high-level synthesis. Proceedings of International Conference on ASIC. IEEE Computer Society, 2013.
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