Timing-aware ATPG for high quality at-speed testing of small delay defects

Xijiang Lin*, Kun Han Tsai, Chen Wang, Mark Kassab, Janusz Rajski, Takeo Kobayashi, Randy Klingenberg, Yasuo Sato, Shuji Hamada, Takashi Aikyo

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

127 Citations (Scopus)


In this paper, a new ATPG methodology is proposed to improve the quality of test sets generated for detecting delay defects. This is achieved by integrating timing information, e.g. from Standard Delay Format (SDF) flies, into the ATPG tool. The timing information is used to guide the test generator to detect faults through the longest paths in order to improve the ability to detect small delay detects. To avoid propagating faults through similar paths repeatedly, a weighted random method is proposed to improve the path coverage during test generation. During fault simulation, a new fault-dropping criterion, named Dropping based on Slack Margin (DSM), is proposed to facilitate the trade-off between the test set quality and the test pattern count. The quality of the generated test set is measured by two metrics: delay test coverage and SDQL. The experimental results show that significant test quality improvement is achieved when applying timing-aware ATPG with DSM to industrial designs.

Original languageEnglish
Title of host publicationProceedings of the 15th Asian Test Symposium 2006
Number of pages8
Publication statusPublished - 2006
Externally publishedYes
Event15th Asian Test Symposium 2006 - Fukuoka, Japan
Duration: 2006 Nov 202006 Nov 23

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735


Conference15th Asian Test Symposium 2006

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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