Timing-aware diagnosis for small delay defects

Takashi Aikyo; Hiroshi Takahashi; Yoshinobu Higami; Junichi Ootsu; Kyohei Ono; Yuzo Takamatsu

doi:10.1109/DFT.2007.30

Timing-aware diagnosis for small delay defects

Takashi Aikyo, Hiroshi Takahashi, Yoshinobu Higami, Junichi Ootsu, Kyohei Ono, Yuzo Takamatsu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

11 Citations (Scopus)

Abstract

As semiconductor technologies progress, testing of small delay defects are becoming more important for SoCs. However, fault diagnosis of small delay defects has not been developed. We propose a novel timing-aware method for diagnosing small delay defects with a small computation cost using gate delay fault simulation with the minimum detectable delay, as introduced in the statistical delay quality model. The experimental results show that the proposed method is capable of identifying fault locations for small delay defects with a small computation cost.

Original language	English
Title of host publication	Proceedings - 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 2007
Pages	223-231
Number of pages	9
DOIs	https://doi.org/10.1109/DFT.2007.30
Publication status	Published - 2007
Externally published	Yes
Event	22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 2007 - Rome, Italy Duration: 2007 Sept 26 → 2007 Sept 28

Publication series

Name	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN (Print)	1550-5774

Conference

Conference	22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 2007
Country/Territory	Italy
City	Rome
Period	07/9/26 → 07/9/28

ASJC Scopus subject areas

Engineering(all)

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10.1109/DFT.2007.30

Cite this

Aikyo, T., Takahashi, H., Higami, Y., Ootsu, J., Ono, K., & Takamatsu, Y. (2007). Timing-aware diagnosis for small delay defects. In Proceedings - 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 2007 (pp. 223-231). [4358391] (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems). https://doi.org/10.1109/DFT.2007.30

Timing-aware diagnosis for small delay defects. / Aikyo, Takashi; Takahashi, Hiroshi; Higami, Yoshinobu et al.

Proceedings - 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 2007. 2007. p. 223-231 4358391 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Aikyo, T, Takahashi, H, Higami, Y, Ootsu, J, Ono, K & Takamatsu, Y 2007, Timing-aware diagnosis for small delay defects. in Proceedings - 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 2007., 4358391, Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 223-231, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 2007, Rome, Italy, 07/9/26. https://doi.org/10.1109/DFT.2007.30

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author = "Takashi Aikyo and Hiroshi Takahashi and Yoshinobu Higami and Junichi Ootsu and Kyohei Ono and Yuzo Takamatsu",

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N2 - As semiconductor technologies progress, testing of small delay defects are becoming more important for SoCs. However, fault diagnosis of small delay defects has not been developed. We propose a novel timing-aware method for diagnosing small delay defects with a small computation cost using gate delay fault simulation with the minimum detectable delay, as introduced in the statistical delay quality model. The experimental results show that the proposed method is capable of identifying fault locations for small delay defects with a small computation cost.

AB - As semiconductor technologies progress, testing of small delay defects are becoming more important for SoCs. However, fault diagnosis of small delay defects has not been developed. We propose a novel timing-aware method for diagnosing small delay defects with a small computation cost using gate delay fault simulation with the minimum detectable delay, as introduced in the statistical delay quality model. The experimental results show that the proposed method is capable of identifying fault locations for small delay defects with a small computation cost.

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BT - Proceedings - 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 2007

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Timing-aware diagnosis for small delay defects

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