Timing-aware diagnosis for small delay defects

Takashi Aikyo, Hiroshi Takahashi, Yoshinobu Higami, Junichi Ootsu, Kyohei Ono, Yuzo Takamatsu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

As semiconductor technologies progress, testing of small delay defects are becoming more important for SoCs. However, fault diagnosis of small delay defects has not been developed. We propose a novel timing-aware method for diagnosing small delay defects with a small computation cost using gate delay fault simulation with the minimum detectable delay, as introduced in the statistical delay quality model. The experimental results show that the proposed method is capable of identifying fault locations for small delay defects with a small computation cost.

Original languageEnglish
Title of host publicationProceedings - 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 2007
Pages223-231
Number of pages9
DOIs
Publication statusPublished - 2007
Externally publishedYes
Event22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 2007 - Rome, Italy
Duration: 2007 Sep 262007 Sep 28

Publication series

NameProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN (Print)1550-5774

Conference

Conference22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 2007
Country/TerritoryItaly
CityRome
Period07/9/2607/9/28

ASJC Scopus subject areas

  • Engineering(all)

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