Timing verification of sequential logic circuits based on controlled multi-clock path analysis

Kazuhiro Nakamura; Shinji Kimura; Kazuyoshi Takagi; Katsumasa Watanabe

Timing verification of sequential logic circuits based on controlled multi-clock path analysis

Kazuhiro Nakamura^*, Shinji Kimura, Kazuyoshi Takagi, Katsumasa Watanabe

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

This paper introduces a new kind of false path, which is sensitizable but does not affect the decision of the maximum clock frequency. Such false paths exist in multi-clock operations controlled by waiting states, and the delay time of these paths can be greater than the clock period. This paper proposes a method to detect these waiting false paths based on the symbolic state traversal. In this method, the maximum allowable clock cycle of each path is computed using update cycles of each register.

Original language	English
Pages (from-to)	2515-2520
Number of pages	6
Journal	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume	E81-A
Issue number	12
Publication status	Published - 1998 Jan 1
Externally published	Yes

Keywords

False path
Maximum delay analysis
Multiple clock operation
Timing verification

ASJC Scopus subject areas

Signal Processing
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering
Applied Mathematics

Cite this

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abstract = "This paper introduces a new kind of false path, which is sensitizable but does not affect the decision of the maximum clock frequency. Such false paths exist in multi-clock operations controlled by waiting states, and the delay time of these paths can be greater than the clock period. This paper proposes a method to detect these waiting false paths based on the symbolic state traversal. In this method, the maximum allowable clock cycle of each path is computed using update cycles of each register.",

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N2 - This paper introduces a new kind of false path, which is sensitizable but does not affect the decision of the maximum clock frequency. Such false paths exist in multi-clock operations controlled by waiting states, and the delay time of these paths can be greater than the clock period. This paper proposes a method to detect these waiting false paths based on the symbolic state traversal. In this method, the maximum allowable clock cycle of each path is computed using update cycles of each register.

AB - This paper introduces a new kind of false path, which is sensitizable but does not affect the decision of the maximum clock frequency. Such false paths exist in multi-clock operations controlled by waiting states, and the delay time of these paths can be greater than the clock period. This paper proposes a method to detect these waiting false paths based on the symbolic state traversal. In this method, the maximum allowable clock cycle of each path is computed using update cycles of each register.

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ER -

Timing verification of sequential logic circuits based on controlled multi-clock path analysis

Abstract

Keywords

ASJC Scopus subject areas

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