Timing verification of sequential logic circuits based on controlled multi-clock path analysis

Kazuhiro Nakamura, Shinji Kimura, Kazuyoshi Takagi, Katsumasa Watanabe

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

This paper introduces a new kind of false path, which is sensitizable but does not affect the decision of the maximum clock frequency. Such false paths exist in multi-clock operations controlled by waiting states, and the delay time of these paths can be greater than the clock period. This paper proposes a method to detect these waiting false paths based on the symbolic state traversal. In this method, the maximum allowable clock cycle of each path is computed using update cycles of each register.

Original languageEnglish
Pages (from-to)2515-2520
Number of pages6
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE81-A
Issue number12
Publication statusPublished - 1998
Externally publishedYes

Fingerprint

Path Analysis
Sequential circuits
Clocks
Timing
Logic
Path
Cycle
Delay Time
Time delay
Update
False

Keywords

  • False path
  • Maximum delay analysis
  • Multiple clock operation
  • Timing verification

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Information Systems

Cite this

Timing verification of sequential logic circuits based on controlled multi-clock path analysis. / Nakamura, Kazuhiro; Kimura, Shinji; Takagi, Kazuyoshi; Watanabe, Katsumasa.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E81-A, No. 12, 1998, p. 2515-2520.

Research output: Contribution to journalArticle

@article{31599a80ab364fd2be78164ed3635b93,
title = "Timing verification of sequential logic circuits based on controlled multi-clock path analysis",
abstract = "This paper introduces a new kind of false path, which is sensitizable but does not affect the decision of the maximum clock frequency. Such false paths exist in multi-clock operations controlled by waiting states, and the delay time of these paths can be greater than the clock period. This paper proposes a method to detect these waiting false paths based on the symbolic state traversal. In this method, the maximum allowable clock cycle of each path is computed using update cycles of each register.",
keywords = "False path, Maximum delay analysis, Multiple clock operation, Timing verification",
author = "Kazuhiro Nakamura and Shinji Kimura and Kazuyoshi Takagi and Katsumasa Watanabe",
year = "1998",
language = "English",
volume = "E81-A",
pages = "2515--2520",
journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
issn = "0916-8508",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "12",

}

TY - JOUR

T1 - Timing verification of sequential logic circuits based on controlled multi-clock path analysis

AU - Nakamura, Kazuhiro

AU - Kimura, Shinji

AU - Takagi, Kazuyoshi

AU - Watanabe, Katsumasa

PY - 1998

Y1 - 1998

N2 - This paper introduces a new kind of false path, which is sensitizable but does not affect the decision of the maximum clock frequency. Such false paths exist in multi-clock operations controlled by waiting states, and the delay time of these paths can be greater than the clock period. This paper proposes a method to detect these waiting false paths based on the symbolic state traversal. In this method, the maximum allowable clock cycle of each path is computed using update cycles of each register.

AB - This paper introduces a new kind of false path, which is sensitizable but does not affect the decision of the maximum clock frequency. Such false paths exist in multi-clock operations controlled by waiting states, and the delay time of these paths can be greater than the clock period. This paper proposes a method to detect these waiting false paths based on the symbolic state traversal. In this method, the maximum allowable clock cycle of each path is computed using update cycles of each register.

KW - False path

KW - Maximum delay analysis

KW - Multiple clock operation

KW - Timing verification

UR - http://www.scopus.com/inward/record.url?scp=0032305823&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032305823&partnerID=8YFLogxK

M3 - Article

VL - E81-A

SP - 2515

EP - 2520

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

SN - 0916-8508

IS - 12

ER -