Topology-aware floorplanning for 3D application-specific Network-on-Chip synthesis

Bo Huang, Song Chen, Wei Zhong, Takeshi Yoshimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

As technology scaling, three-dimensional integrated circuits (3D-ICs) are emerging as a promising solution to address the challenges in system on chips (SoCs). Moreover, it's a necessity to design an efficient Network-on-Chip (NoC) topology for the interconnection issues of 3D SoCs. In this paper, we propose a topology-aware floorplanning method to determine the power-performance efficient 3D NoC topology. Unlike the previous works which explore the path allocation of the NoC components and Through-Silicon Vias (TSVs) assignment after the floorplan of cores is fixed, we integrate these steps (the clustering of cores + the placement of cores and switches + the path allocation + the TSV-aware topology evaluation) within the 3D floorplanning procedure. Experimental results show the effectiveness of our method.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Pages1732-1735
Number of pages4
DOIs
Publication statusPublished - 2013
Event2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing
Duration: 2013 May 192013 May 23

Other

Other2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
CityBeijing
Period13/5/1913/5/23

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Huang, B., Chen, S., Zhong, W., & Yoshimura, T. (2013). Topology-aware floorplanning for 3D application-specific Network-on-Chip synthesis. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 1732-1735). [6572199] https://doi.org/10.1109/ISCAS.2013.6572199