Topology-Based Exact Synthesis for Majority Inverter Graph

Xianliang Ge, Shinji Kimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

SAT-based exact synthesis has important applications in logic optimization problems, and its scalability and computational speed greatly affect the optimization results. In the paper, a new topological constraint using the list of levels of inputs of each gate is introduced and accelerates the exact synthesis. Such topological constraints can reduce the search space by structure enumeration. By our new partition of the synthesis problem, we can maintain a good balance between runtime on a single satisfiability problem and the number of satisfiability problems. When compared to the fence-based method and the partial DAG based method, our methodology demonstrates a considerable reduction in runtime of 24.5% and 5.7%, respectively. Furthermore, our implementation can extend the scalability of SAT-based exact synthesis.

Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and Systems, ISCAS 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages3255-3259
Number of pages5
ISBN (Electronic)9781665484855
DOIs
Publication statusPublished - 2022
Event2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022 - Austin, United States
Duration: 2022 May 272022 Jun 1

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2022-May
ISSN (Print)0271-4310

Conference

Conference2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022
Country/TerritoryUnited States
CityAustin
Period22/5/2722/6/1

Keywords

  • Logic synthesis
  • Majority synthesis
  • Majority-Inverter Graph
  • Satisfiability
  • Topology

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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