Twisted bit-line architectures for multi-megabit DRAM's

Hideto Hidaka*, Kazuyasu Fujishima, Yoshio Matsuda, Mikio Asakura, Tsutomu Yoshihara

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

51 Citations (Scopus)


As the memory cell array of DRAM has been scaled down, inter-bit-line coupling noise has emerged as a serious problem. The signal loss due to this noise is estimated at about 40% of the signal amplitude in a polycide-bit-line 16-Mb DRAM with a technologically attainable scaling scheme. Twisted bit-line architectures to reduce or eliminate the noise are proposed and demonstrated by the soft-error rate improvement of a 1-Mb DRAM. The effective critical charge is improved by 35%, which is attributed not only to the improvement of the signal amplitude but also to the elimination of large coupling noise during the sensing operation. The impact of these twisted bit-line architectures from a scaling viewpoint is also examined, and they are shown to be promising candidates for overcoming the scaling problems of DRAMs.

Original languageEnglish
Pages (from-to)21-27
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Issue number1
Publication statusPublished - 1989 Feb
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


Dive into the research topics of 'Twisted bit-line architectures for multi-megabit DRAM's'. Together they form a unique fingerprint.

Cite this