Abstract
The authors propose and demonstrate bitline architecture to eliminate the noise and also overcome the scaling problem of future dynamic random-access memories (DRAMs). Twisted bit line (TBL) techniques which cancel the interbitline coupling noise and improve the signal are described. The interpair coupling noise in the TBL configurations is equally coupled to adjacent paired bitlines and cancelled in the differential sensing operation. In the modified TBL case, the intrapair coupling noise is also eliminated and the signal is improved twice as much as in the TBL case. Thus, in the modified TBL, the bitline-bitline coupling capacitance does not cause coupling noise, but only increases the total bitline capacitance. To demonstrate the effects of the TBL methods, a TBL structure is implemented on a 1-Mb DRAM without layout constraints.
| Original language | English |
|---|---|
| Title of host publication | Digest of Technical Papers - IEEE International Solid-State Circuits Conference |
| Publisher | Publ by IEEE |
| Pages | 238-239 |
| Number of pages | 2 |
| Volume | 31 |
| Publication status | Published - 1988 |
| Externally published | Yes |
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ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
Twisted bit line technique for multi-Mb DRAMS. / Yoshihara, Tsutomu; Hidaka, Hideto; Matsuda, Yoshio; Fujishima, Kazuyasu.
Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 31 Publ by IEEE, 1988. p. 238-239.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Twisted bit line technique for multi-Mb DRAMS.
AU - Yoshihara, Tsutomu
AU - Hidaka, Hideto
AU - Matsuda, Yoshio
AU - Fujishima, Kazuyasu
PY - 1988
Y1 - 1988
N2 - The authors propose and demonstrate bitline architecture to eliminate the noise and also overcome the scaling problem of future dynamic random-access memories (DRAMs). Twisted bit line (TBL) techniques which cancel the interbitline coupling noise and improve the signal are described. The interpair coupling noise in the TBL configurations is equally coupled to adjacent paired bitlines and cancelled in the differential sensing operation. In the modified TBL case, the intrapair coupling noise is also eliminated and the signal is improved twice as much as in the TBL case. Thus, in the modified TBL, the bitline-bitline coupling capacitance does not cause coupling noise, but only increases the total bitline capacitance. To demonstrate the effects of the TBL methods, a TBL structure is implemented on a 1-Mb DRAM without layout constraints.
AB - The authors propose and demonstrate bitline architecture to eliminate the noise and also overcome the scaling problem of future dynamic random-access memories (DRAMs). Twisted bit line (TBL) techniques which cancel the interbitline coupling noise and improve the signal are described. The interpair coupling noise in the TBL configurations is equally coupled to adjacent paired bitlines and cancelled in the differential sensing operation. In the modified TBL case, the intrapair coupling noise is also eliminated and the signal is improved twice as much as in the TBL case. Thus, in the modified TBL, the bitline-bitline coupling capacitance does not cause coupling noise, but only increases the total bitline capacitance. To demonstrate the effects of the TBL methods, a TBL structure is implemented on a 1-Mb DRAM without layout constraints.
UR - http://www.scopus.com/inward/record.url?scp=0024134001&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0024134001&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0024134001
VL - 31
SP - 238
EP - 239
BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
PB - Publ by IEEE
ER -