Twisted bit line technique for multi-Mb DRAMS.

Tsutomu Yoshihara, Hideto Hidaka, Yoshio Matsuda, Kazuyasu Fujishima

Research output: Chapter in Book/Report/Conference proceedingConference contribution

24 Citations (Scopus)

Abstract

The authors propose and demonstrate bitline architecture to eliminate the noise and also overcome the scaling problem of future dynamic random-access memories (DRAMs). Twisted bit line (TBL) techniques which cancel the interbitline coupling noise and improve the signal are described. The interpair coupling noise in the TBL configurations is equally coupled to adjacent paired bitlines and cancelled in the differential sensing operation. In the modified TBL case, the intrapair coupling noise is also eliminated and the signal is improved twice as much as in the TBL case. Thus, in the modified TBL, the bitline-bitline coupling capacitance does not cause coupling noise, but only increases the total bitline capacitance. To demonstrate the effects of the TBL methods, a TBL structure is implemented on a 1-Mb DRAM without layout constraints.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
PublisherPubl by IEEE
Pages238-239
Number of pages2
Volume31
Publication statusPublished - 1988
Externally publishedYes

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Yoshihara, T., Hidaka, H., Matsuda, Y., & Fujishima, K. (1988). Twisted bit line technique for multi-Mb DRAMS. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference (Vol. 31, pp. 238-239). Publ by IEEE.