Ultra-high-speed and low-power SOI CMOS technology with body-tied hybrid trench isolation structure

Yuuichi Hirano, Takashi Ipposhi, Dang Hai Thai, Toshiaki Iwamatsu, Tatsuhiko Ikeda, Mikio Tsujiuchi, Shigeto Maegawa, Masahide Inuishi, Yuzuru Ohji

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The hybrid-trench-isolation (HTI) SOI technology overcomes the scaling limitations caused by the difficulty of the gate thinning. A high-speed and low-power microcontroller including logic, memory, analog, and PLL circuits has been demonstrated by using the HTI SOI technology with bulk-layout compatibility. Over 10Gbps and low-noise operation with excellent eye patterns of output buffer circuits were also obtained for ultra-high-speed network LSIs. It is also verified that low-voltage and high-speed operation is achieved for an Actively Body-bias Controlled (ABC) SOI SRAM that has a new cell structure connecting the bodies of the access and the driver transistors with the word line. It is concluded that the SOI technology with the HTI structure is one of the solutions against the scaling limitations.

Original languageEnglish
Title of host publicationDielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - proceedings of the First International Symposium
EditorsR. Singh, H. Iwai, R.R. Tummala, S.C. Sun
Pages60-64
Number of pages5
Volume4
Publication statusPublished - 2004
Externally publishedYes
EventDielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - Proceedings of the First International Symposium - Honolulu, HI, United States
Duration: 2004 Oct 32004 Oct 8

Other

OtherDielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - Proceedings of the First International Symposium
CountryUnited States
CityHonolulu, HI
Period04/10/304/10/8

Fingerprint

Buffer circuits
HIgh speed networks
Static random access storage
Phase locked loops
Microcontrollers
Transistors
Data storage equipment
Networks (circuits)
Electric potential

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Hirano, Y., Ipposhi, T., Thai, D. H., Iwamatsu, T., Ikeda, T., Tsujiuchi, M., ... Ohji, Y. (2004). Ultra-high-speed and low-power SOI CMOS technology with body-tied hybrid trench isolation structure. In R. Singh, H. Iwai, R. R. Tummala, & S. C. Sun (Eds.), Dielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - proceedings of the First International Symposium (Vol. 4, pp. 60-64)

Ultra-high-speed and low-power SOI CMOS technology with body-tied hybrid trench isolation structure. / Hirano, Yuuichi; Ipposhi, Takashi; Thai, Dang Hai; Iwamatsu, Toshiaki; Ikeda, Tatsuhiko; Tsujiuchi, Mikio; Maegawa, Shigeto; Inuishi, Masahide; Ohji, Yuzuru.

Dielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - proceedings of the First International Symposium. ed. / R. Singh; H. Iwai; R.R. Tummala; S.C. Sun. Vol. 4 2004. p. 60-64.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hirano, Y, Ipposhi, T, Thai, DH, Iwamatsu, T, Ikeda, T, Tsujiuchi, M, Maegawa, S, Inuishi, M & Ohji, Y 2004, Ultra-high-speed and low-power SOI CMOS technology with body-tied hybrid trench isolation structure. in R Singh, H Iwai, RR Tummala & SC Sun (eds), Dielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - proceedings of the First International Symposium. vol. 4, pp. 60-64, Dielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - Proceedings of the First International Symposium, Honolulu, HI, United States, 04/10/3.
Hirano Y, Ipposhi T, Thai DH, Iwamatsu T, Ikeda T, Tsujiuchi M et al. Ultra-high-speed and low-power SOI CMOS technology with body-tied hybrid trench isolation structure. In Singh R, Iwai H, Tummala RR, Sun SC, editors, Dielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - proceedings of the First International Symposium. Vol. 4. 2004. p. 60-64
Hirano, Yuuichi ; Ipposhi, Takashi ; Thai, Dang Hai ; Iwamatsu, Toshiaki ; Ikeda, Tatsuhiko ; Tsujiuchi, Mikio ; Maegawa, Shigeto ; Inuishi, Masahide ; Ohji, Yuzuru. / Ultra-high-speed and low-power SOI CMOS technology with body-tied hybrid trench isolation structure. Dielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - proceedings of the First International Symposium. editor / R. Singh ; H. Iwai ; R.R. Tummala ; S.C. Sun. Vol. 4 2004. pp. 60-64
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AU - Ikeda, Tatsuhiko

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