The hybrid-trench-isolation (HTI) SOI technology overcomes the scaling limitations caused by the difficulty of the gate thinning. A high-speed and low-power microcontroller including logic, memory, analog, and PLL circuits has been demonstrated by using the HTI SOI technology with bulk-layout compatibility. Over 10Gbps and low-noise operation with excellent eye patterns of output buffer circuits were also obtained for ultra-high-speed network LSIs. It is also verified that low-voltage and high-speed operation is achieved for an Actively Body-bias Controlled (ABC) SOI SRAM that has a new cell structure connecting the bodies of the access and the driver transistors with the word line. It is concluded that the SOI technology with the HTI structure is one of the solutions against the scaling limitations.
|Number of pages||5|
|Publication status||Published - 2004 Dec 1|
|Event||Dielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - Proceedings of the First International Symposium - Honolulu, HI, United States|
Duration: 2004 Oct 3 → 2004 Oct 8
|Other||Dielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - Proceedings of the First International Symposium|
|Period||04/10/3 → 04/10/8|
ASJC Scopus subject areas