Ultra low power QC-LDPC decoder with high parallelism

Ying Cui, Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Yichao Lu, Dajiang Zhou, Satoshi Goto

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    6 Citations (Scopus)

    Abstract

    This paper presents a novel high parallel decoder architecture for the quasi-cyclic low-density parity-check (QC-LDPC) codes defined in WiMAX system. Based on the turbo-decoding message passing (TDMP) algorithm, this architecture costs 816 clock cycles for each iteration in the decoding process. In the normalized comparison with the state-of-art work, this design achieves up to 6.5 higher parallelism and 76% power reduction. The energy/bit/iteration of this design is only 1/5 of the previous work.

    Original languageEnglish
    Title of host publicationInternational System on Chip Conference
    Pages142-145
    Number of pages4
    DOIs
    Publication statusPublished - 2011
    Event24th IEEE International System on Chip Conference, SOCC 2011 - Taipei
    Duration: 2011 Sep 262011 Sep 28

    Other

    Other24th IEEE International System on Chip Conference, SOCC 2011
    CityTaipei
    Period11/9/2611/9/28

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Control and Systems Engineering
    • Electrical and Electronic Engineering

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  • Cite this

    Cui, Y., Peng, X., Chen, Z., Zhao, X., Lu, Y., Zhou, D., & Goto, S. (2011). Ultra low power QC-LDPC decoder with high parallelism. In International System on Chip Conference (pp. 142-145). [6085136] https://doi.org/10.1109/SOCC.2011.6085136