Ultra-shallow junction formation by non-melt laser spike annealing for 50-nm gate CMOS

Akio Shima; Yun Wang; Somit Talwar; Atsushi Hiraiwa

Ultra-shallow junction formation by non-melt laser spike annealing for 50-nm gate CMOS

Akio Shima^*, Yun Wang, Somit Talwar, Atsushi Hiraiwa

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

57 Citations (Scopus)

Abstract

We activated source/drain junctions of CMOS by simply replacing RTA in the conventional production flow by non-melt laser spike annealing (LSA). We did not form any additional layers unlike the conventional laser annealing. The 50-nm gate CMOS devices thus formed had overwhelmingly better Vth roll-offs and larger drain currents compared to those by RTA. We found that the LSA-devices without offset spacers had better performance than those with offset spacers, and that the optimization of the overlap length between the gate and source/drain extensions was important due to the minimal lateral diffusion during the sub-millisecond annealing of LSA.

Original language	English
Title of host publication	Digest of Technical Papers - Symposium on VLSI Technology
Pages	174-175
Number of pages	2
Publication status	Published - 2004
Externally published	Yes
Event	2004 Symposium on VLSI Technology - Digest of Technical Papers - Honolulu, HI, United States Duration: 2004 Jun 15 → 2004 Jun 17

Other

Other	2004 Symposium on VLSI Technology - Digest of Technical Papers
Country/Territory	United States
City	Honolulu, HI
Period	04/6/15 → 04/6/17

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "Ultra-shallow junction formation by non-melt laser spike annealing for 50-nm gate CMOS",

abstract = "We activated source/drain junctions of CMOS by simply replacing RTA in the conventional production flow by non-melt laser spike annealing (LSA). We did not form any additional layers unlike the conventional laser annealing. The 50-nm gate CMOS devices thus formed had overwhelmingly better Vth roll-offs and larger drain currents compared to those by RTA. We found that the LSA-devices without offset spacers had better performance than those with offset spacers, and that the optimization of the overlap length between the gate and source/drain extensions was important due to the minimal lateral diffusion during the sub-millisecond annealing of LSA.",

author = "Akio Shima and Yun Wang and Somit Talwar and Atsushi Hiraiwa",

year = "2004",

language = "English",

pages = "174--175",

booktitle = "Digest of Technical Papers - Symposium on VLSI Technology",

note = "2004 Symposium on VLSI Technology - Digest of Technical Papers ; Conference date: 15-06-2004 Through 17-06-2004",

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T1 - Ultra-shallow junction formation by non-melt laser spike annealing for 50-nm gate CMOS

AU - Shima, Akio

AU - Wang, Yun

AU - Talwar, Somit

AU - Hiraiwa, Atsushi

PY - 2004

Y1 - 2004

N2 - We activated source/drain junctions of CMOS by simply replacing RTA in the conventional production flow by non-melt laser spike annealing (LSA). We did not form any additional layers unlike the conventional laser annealing. The 50-nm gate CMOS devices thus formed had overwhelmingly better Vth roll-offs and larger drain currents compared to those by RTA. We found that the LSA-devices without offset spacers had better performance than those with offset spacers, and that the optimization of the overlap length between the gate and source/drain extensions was important due to the minimal lateral diffusion during the sub-millisecond annealing of LSA.

AB - We activated source/drain junctions of CMOS by simply replacing RTA in the conventional production flow by non-melt laser spike annealing (LSA). We did not form any additional layers unlike the conventional laser annealing. The 50-nm gate CMOS devices thus formed had overwhelmingly better Vth roll-offs and larger drain currents compared to those by RTA. We found that the LSA-devices without offset spacers had better performance than those with offset spacers, and that the optimization of the overlap length between the gate and source/drain extensions was important due to the minimal lateral diffusion during the sub-millisecond annealing of LSA.

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M3 - Conference contribution

AN - SCOPUS:4544244756

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EP - 175

BT - Digest of Technical Papers - Symposium on VLSI Technology

T2 - 2004 Symposium on VLSI Technology - Digest of Technical Papers

Y2 - 15 June 2004 through 17 June 2004

ER -

Ultra-shallow junction formation by non-melt laser spike annealing for 50-nm gate CMOS

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