Ultra-shallow junction formation by non-melt laser spike annealing for 50-nm gate CMOS

Akio Shima, Yun Wang, Somit Talwar, Atsushi Hiraiwa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

48 Citations (Scopus)

Abstract

We activated source/drain junctions of CMOS by simply replacing RTA in the conventional production flow by non-melt laser spike annealing (LSA). We did not form any additional layers unlike the conventional laser annealing. The 50-nm gate CMOS devices thus formed had overwhelmingly better Vth roll-offs and larger drain currents compared to those by RTA. We found that the LSA-devices without offset spacers had better performance than those with offset spacers, and that the optimization of the overlap length between the gate and source/drain extensions was important due to the minimal lateral diffusion during the sub-millisecond annealing of LSA.

Original languageEnglish
Title of host publicationDigest of Technical Papers - Symposium on VLSI Technology
Pages174-175
Number of pages2
Publication statusPublished - 2004
Externally publishedYes
Event2004 Symposium on VLSI Technology - Digest of Technical Papers - Honolulu, HI, United States
Duration: 2004 Jun 152004 Jun 17

Other

Other2004 Symposium on VLSI Technology - Digest of Technical Papers
CountryUnited States
CityHonolulu, HI
Period04/6/1504/6/17

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Ultra-shallow junction formation by non-melt laser spike annealing for 50-nm gate CMOS'. Together they form a unique fingerprint.

  • Cite this

    Shima, A., Wang, Y., Talwar, S., & Hiraiwa, A. (2004). Ultra-shallow junction formation by non-melt laser spike annealing for 50-nm gate CMOS. In Digest of Technical Papers - Symposium on VLSI Technology (pp. 174-175)