Ultra-shallow junction formation by non-melt laser spike annealing and its application to complementary metal oxide semiconductor devices in 65-nm node

Akio Shima, Atsushi Hiraiwa

Research output: Contribution to journalArticle

40 Citations (Scopus)

Abstract

We activated source/drain junctions of complementary metal oxide semiconductor (CMOS) by simply replacing rapid thermal annealing (RTA) in the conventional production flow by non-melt laser spike annealing (LSA). We did not form any additional layers, unlike the conventional laser annealing. The 50-nm gate CMOS devices thus formed had overwhelmingly better Vth roll-offs and larger drain currents compared to those formed by RTA. We found that the LSA-devices without offset spacers had better performance than those with offset spacers, and that the optimization of the overlap length between the gate and source/drain extensions was important due to the minimal lateral diffusion during the sub-millisecond annealing of LSA.

Original languageEnglish
Pages (from-to)5708-5715
Number of pages8
JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume45
Issue number7
DOIs
Publication statusPublished - 2006 Jul 7
Externally publishedYes

Fingerprint

MOS devices
semiconductor devices
spikes
CMOS
Annealing
annealing
Lasers
Rapid thermal annealing
lasers
spacers
Drain current
laser annealing
Metals
optimization

Keywords

  • Laser annealing
  • Pre-amorphlzatlon implantation
  • Source/drain extensions
  • Sub-millisecond annealing
  • Ultra-shallow junction

ASJC Scopus subject areas

  • Physics and Astronomy (miscellaneous)

Cite this

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