Ultralow-voltage operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM down to 0.37 v utilizing adaptive back bias

Y. Yamamoto, H. Makiyama, Hirofumi Shinohara, T. Iwamatsu, H. Oda, S. Kamohara, N. Sugii, Y. Yamaguchi, T. Mizutani, T. Hiramoto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Abstract

We demonstrated record 0.37V minimum operation voltage (Vmin) of 2Mb Silicon-on-Thin-Buried-oxide (SOTB) 6T-SRAM. Thanks to the small variability of SOTB (AVT∼1.3 mVμm) and adaptive back biasing (ABB), Vmin was lowered down to ∼0.4 V regardless of temperature. Both fast access time and small standby leakage were achieved by ABB.

Original languageEnglish
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Publication statusPublished - 2013
Externally publishedYes
Event2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan
Duration: 2013 Jun 122013 Jun 14

Other

Other2013 Symposium on VLSI Circuits, VLSIC 2013
CountryJapan
CityKyoto
Period13/6/1213/6/14

Fingerprint

Static random access storage
Silicon
Electric potential
Oxides
Temperature

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Yamamoto, Y., Makiyama, H., Shinohara, H., Iwamatsu, T., Oda, H., Kamohara, S., ... Hiramoto, T. (2013). Ultralow-voltage operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM down to 0.37 v utilizing adaptive back bias. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers [6578753]

Ultralow-voltage operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM down to 0.37 v utilizing adaptive back bias. / Yamamoto, Y.; Makiyama, H.; Shinohara, Hirofumi; Iwamatsu, T.; Oda, H.; Kamohara, S.; Sugii, N.; Yamaguchi, Y.; Mizutani, T.; Hiramoto, T.

IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2013. 6578753.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yamamoto, Y, Makiyama, H, Shinohara, H, Iwamatsu, T, Oda, H, Kamohara, S, Sugii, N, Yamaguchi, Y, Mizutani, T & Hiramoto, T 2013, Ultralow-voltage operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM down to 0.37 v utilizing adaptive back bias. in IEEE Symposium on VLSI Circuits, Digest of Technical Papers., 6578753, 2013 Symposium on VLSI Circuits, VLSIC 2013, Kyoto, Japan, 13/6/12.
Yamamoto Y, Makiyama H, Shinohara H, Iwamatsu T, Oda H, Kamohara S et al. Ultralow-voltage operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM down to 0.37 v utilizing adaptive back bias. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2013. 6578753
Yamamoto, Y. ; Makiyama, H. ; Shinohara, Hirofumi ; Iwamatsu, T. ; Oda, H. ; Kamohara, S. ; Sugii, N. ; Yamaguchi, Y. ; Mizutani, T. ; Hiramoto, T. / Ultralow-voltage operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM down to 0.37 v utilizing adaptive back bias. IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2013.
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