Unified parameter decoder architecture for H.265/HEVC motion vector and boundary strength decoding

Shihao Wang, Dajiang Zhou, Jianbin Zhou, Takeshi Yoshimura, Satoshi Goto

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

In this paper, VLSI architecture design of unified motion vector (MV) and boundary strength (BS) parameter decoder (PDec) for 8K UHDTV HEVC decoder is presented. The adoption of new coding tools in PDec, such as Advanced Motion Vector Prediction (AMVP), increases the VLSI hardware realization overhead and memory bandwidth requirement, especially for 8K UHDTV application. We propose four techniques for these challenges. Firstly, this work unifies MV and BS parameter decoders for line buffer memory sharing. Secondly, to support high throughput, we propose the top-level CU-adaptive pipeline scheme by trading off between implementation complexity and performance. Thirdly, PDec process engine with optimizations is adopted for 43.2k area reduction. Finally, PU-based coding scheme is proposed for 30% DRAM bandwidth reduction. In 90 nm process, our design costs 93.3k logic gates with 23.0 kB line buffer. The proposed architecture can support real-time decoding for 7680x4320@60fps application at 249MHz in the worst case.

Original languageEnglish
Pages (from-to)1356-1365
Number of pages10
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE98A
Issue number7
DOIs
Publication statusPublished - 2015 Jul 1

Fingerprint

Motion Vector
Decoding
Buffer
Coding
Bandwidth
VLSI Architecture
Data storage equipment
Process Design
Logic gates
Line
Dynamic random access storage
Process Parameters
Computer hardware
High Throughput
Sharing
Engine
Pipelines
Throughput
Hardware
Logic

Keywords

  • Boundary strength
  • H.265/HEVC
  • Motion vector
  • Parameter decoder
  • UHDTV

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Graphics and Computer-Aided Design
  • Applied Mathematics
  • Signal Processing

Cite this

Unified parameter decoder architecture for H.265/HEVC motion vector and boundary strength decoding. / Wang, Shihao; Zhou, Dajiang; Zhou, Jianbin; Yoshimura, Takeshi; Goto, Satoshi.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E98A, No. 7, 01.07.2015, p. 1356-1365.

Research output: Contribution to journalArticle

Wang, Shihao ; Zhou, Dajiang ; Zhou, Jianbin ; Yoshimura, Takeshi ; Goto, Satoshi. / Unified parameter decoder architecture for H.265/HEVC motion vector and boundary strength decoding. In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2015 ; Vol. E98A, No. 7. pp. 1356-1365.
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