Unified VLSI architecture of motion vector and boundary strength parameter decoder for 8K UHDTV HEVC decoder

Shihao Wang, Dajiang Zhou, Jianbin Zhou, Takeshi Yoshimura, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper presents a VLSI architecture design of unified motion vector (MV) and boundary strength (BS) parameter decoder (PDec) for 8K UHDTV HEVC decoder. PDec in HEVC is deemed as a highly algorithm-irregular module, which is also challenged by high throughput requirement for UHDTV. To solve these problems, four schemes are proposed. Firstly, the work unifies MV and BS parameter decoders to share on-chip memory and simplify the control logic. Secondly, we propose the CU-adaptive pipeline scheme to efficiently reduce the implementation complexity. Thirdly, on-chip memory is organized to meet the high throughput requirement for spatial neighboring fetching. Finally, optimizations on irregular MV algorithm are adopted for 43.2k area reduction. In 90nm process, our design costs 93.3k logic gates with 23.0kB line buffer. The proposed architecture can support 7680x4320@60fps realtime decoding at 249MHz in the worst case.

Original languageEnglish
Title of host publicationLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
PublisherSpringer Verlag
Pages74-83
Number of pages10
Volume8879
ISBN (Print)9783319131672
Publication statusPublished - 2014
Event15th Pacific-Rim Conference on Multimedia, PCM 2014 - Kuching
Duration: 2014 Dec 12014 Dec 4

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume8879
ISSN (Print)03029743
ISSN (Electronic)16113349

Other

Other15th Pacific-Rim Conference on Multimedia, PCM 2014
CityKuching
Period14/12/114/12/4

Fingerprint

VLSI Architecture
Motion Vector
High Throughput
Irregular
Chip
Throughput
Logic
Data storage equipment
Process Design
Logic gates
Requirements
Decoding
Buffer
Simplify
Pipelines
Real-time
Module
Optimization
Line
Costs

Keywords

  • Boundary strength
  • HEVC
  • Motion vector
  • Parameter decoder
  • Real-time decoding
  • UHDTV

ASJC Scopus subject areas

  • Computer Science(all)
  • Theoretical Computer Science

Cite this

Wang, S., Zhou, D., Zhou, J., Yoshimura, T., & Goto, S. (2014). Unified VLSI architecture of motion vector and boundary strength parameter decoder for 8K UHDTV HEVC decoder. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (Vol. 8879, pp. 74-83). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 8879). Springer Verlag.

Unified VLSI architecture of motion vector and boundary strength parameter decoder for 8K UHDTV HEVC decoder. / Wang, Shihao; Zhou, Dajiang; Zhou, Jianbin; Yoshimura, Takeshi; Goto, Satoshi.

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 8879 Springer Verlag, 2014. p. 74-83 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 8879).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wang, S, Zhou, D, Zhou, J, Yoshimura, T & Goto, S 2014, Unified VLSI architecture of motion vector and boundary strength parameter decoder for 8K UHDTV HEVC decoder. in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). vol. 8879, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 8879, Springer Verlag, pp. 74-83, 15th Pacific-Rim Conference on Multimedia, PCM 2014, Kuching, 14/12/1.
Wang S, Zhou D, Zhou J, Yoshimura T, Goto S. Unified VLSI architecture of motion vector and boundary strength parameter decoder for 8K UHDTV HEVC decoder. In Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 8879. Springer Verlag. 2014. p. 74-83. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).
Wang, Shihao ; Zhou, Dajiang ; Zhou, Jianbin ; Yoshimura, Takeshi ; Goto, Satoshi. / Unified VLSI architecture of motion vector and boundary strength parameter decoder for 8K UHDTV HEVC decoder. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Vol. 8879 Springer Verlag, 2014. pp. 74-83 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).
@inproceedings{cf0876a2e67c42b8b0936f62e3082812,
title = "Unified VLSI architecture of motion vector and boundary strength parameter decoder for 8K UHDTV HEVC decoder",
abstract = "This paper presents a VLSI architecture design of unified motion vector (MV) and boundary strength (BS) parameter decoder (PDec) for 8K UHDTV HEVC decoder. PDec in HEVC is deemed as a highly algorithm-irregular module, which is also challenged by high throughput requirement for UHDTV. To solve these problems, four schemes are proposed. Firstly, the work unifies MV and BS parameter decoders to share on-chip memory and simplify the control logic. Secondly, we propose the CU-adaptive pipeline scheme to efficiently reduce the implementation complexity. Thirdly, on-chip memory is organized to meet the high throughput requirement for spatial neighboring fetching. Finally, optimizations on irregular MV algorithm are adopted for 43.2k area reduction. In 90nm process, our design costs 93.3k logic gates with 23.0kB line buffer. The proposed architecture can support 7680x4320@60fps realtime decoding at 249MHz in the worst case.",
keywords = "Boundary strength, HEVC, Motion vector, Parameter decoder, Real-time decoding, UHDTV",
author = "Shihao Wang and Dajiang Zhou and Jianbin Zhou and Takeshi Yoshimura and Satoshi Goto",
year = "2014",
language = "English",
isbn = "9783319131672",
volume = "8879",
series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
publisher = "Springer Verlag",
pages = "74--83",
booktitle = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

}

TY - GEN

T1 - Unified VLSI architecture of motion vector and boundary strength parameter decoder for 8K UHDTV HEVC decoder

AU - Wang, Shihao

AU - Zhou, Dajiang

AU - Zhou, Jianbin

AU - Yoshimura, Takeshi

AU - Goto, Satoshi

PY - 2014

Y1 - 2014

N2 - This paper presents a VLSI architecture design of unified motion vector (MV) and boundary strength (BS) parameter decoder (PDec) for 8K UHDTV HEVC decoder. PDec in HEVC is deemed as a highly algorithm-irregular module, which is also challenged by high throughput requirement for UHDTV. To solve these problems, four schemes are proposed. Firstly, the work unifies MV and BS parameter decoders to share on-chip memory and simplify the control logic. Secondly, we propose the CU-adaptive pipeline scheme to efficiently reduce the implementation complexity. Thirdly, on-chip memory is organized to meet the high throughput requirement for spatial neighboring fetching. Finally, optimizations on irregular MV algorithm are adopted for 43.2k area reduction. In 90nm process, our design costs 93.3k logic gates with 23.0kB line buffer. The proposed architecture can support 7680x4320@60fps realtime decoding at 249MHz in the worst case.

AB - This paper presents a VLSI architecture design of unified motion vector (MV) and boundary strength (BS) parameter decoder (PDec) for 8K UHDTV HEVC decoder. PDec in HEVC is deemed as a highly algorithm-irregular module, which is also challenged by high throughput requirement for UHDTV. To solve these problems, four schemes are proposed. Firstly, the work unifies MV and BS parameter decoders to share on-chip memory and simplify the control logic. Secondly, we propose the CU-adaptive pipeline scheme to efficiently reduce the implementation complexity. Thirdly, on-chip memory is organized to meet the high throughput requirement for spatial neighboring fetching. Finally, optimizations on irregular MV algorithm are adopted for 43.2k area reduction. In 90nm process, our design costs 93.3k logic gates with 23.0kB line buffer. The proposed architecture can support 7680x4320@60fps realtime decoding at 249MHz in the worst case.

KW - Boundary strength

KW - HEVC

KW - Motion vector

KW - Parameter decoder

KW - Real-time decoding

KW - UHDTV

UR - http://www.scopus.com/inward/record.url?scp=84910116309&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84910116309&partnerID=8YFLogxK

M3 - Conference contribution

SN - 9783319131672

VL - 8879

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 74

EP - 83

BT - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

PB - Springer Verlag

ER -