Variation-aware subthreshold logic circuit design

Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Subthreshold logic circuits are one of promising solutions to achieve ultra-low power operation. However, subthreshold circuits are significantly sensitive to manufacturing and environmental variability. In this paper, we will discuss design challenges in subthreshold logic circuits, such as rise in a minimum operating voltage, signal integrity degradation, and large delay variations.

Original languageEnglish
Title of host publicationProceedings of International Conference on ASIC
PublisherIEEE Computer Society
ISBN (Print)9781467364157
DOIs
Publication statusPublished - 2013
Externally publishedYes
Event2013 IEEE 10th International Conference on ASIC, ASICON 2013 - Shenzhen, China
Duration: 2013 Oct 282013 Oct 31

Other

Other2013 IEEE 10th International Conference on ASIC, ASICON 2013
CountryChina
CityShenzhen
Period13/10/2813/10/31

Fingerprint

Logic design
Logic circuits
Degradation
Networks (circuits)
Electric potential

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Fuketa, H., Takahashi, R., Takamiya, M., Nomura, M., Shinohara, H., & Sakurai, T. (2013). Variation-aware subthreshold logic circuit design. In Proceedings of International Conference on ASIC [6811842] IEEE Computer Society. https://doi.org/10.1109/ASICON.2013.6811842

Variation-aware subthreshold logic circuit design. / Fuketa, Hiroshi; Takahashi, Ryo; Takamiya, Makoto; Nomura, Masahiro; Shinohara, Hirofumi; Sakurai, Takayasu.

Proceedings of International Conference on ASIC. IEEE Computer Society, 2013. 6811842.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fuketa, H, Takahashi, R, Takamiya, M, Nomura, M, Shinohara, H & Sakurai, T 2013, Variation-aware subthreshold logic circuit design. in Proceedings of International Conference on ASIC., 6811842, IEEE Computer Society, 2013 IEEE 10th International Conference on ASIC, ASICON 2013, Shenzhen, China, 13/10/28. https://doi.org/10.1109/ASICON.2013.6811842
Fuketa H, Takahashi R, Takamiya M, Nomura M, Shinohara H, Sakurai T. Variation-aware subthreshold logic circuit design. In Proceedings of International Conference on ASIC. IEEE Computer Society. 2013. 6811842 https://doi.org/10.1109/ASICON.2013.6811842
Fuketa, Hiroshi ; Takahashi, Ryo ; Takamiya, Makoto ; Nomura, Masahiro ; Shinohara, Hirofumi ; Sakurai, Takayasu. / Variation-aware subthreshold logic circuit design. Proceedings of International Conference on ASIC. IEEE Computer Society, 2013.
@inproceedings{7c32aef6740e4634881260882ed8bd22,
title = "Variation-aware subthreshold logic circuit design",
abstract = "Subthreshold logic circuits are one of promising solutions to achieve ultra-low power operation. However, subthreshold circuits are significantly sensitive to manufacturing and environmental variability. In this paper, we will discuss design challenges in subthreshold logic circuits, such as rise in a minimum operating voltage, signal integrity degradation, and large delay variations.",
author = "Hiroshi Fuketa and Ryo Takahashi and Makoto Takamiya and Masahiro Nomura and Hirofumi Shinohara and Takayasu Sakurai",
year = "2013",
doi = "10.1109/ASICON.2013.6811842",
language = "English",
isbn = "9781467364157",
booktitle = "Proceedings of International Conference on ASIC",
publisher = "IEEE Computer Society",

}

TY - GEN

T1 - Variation-aware subthreshold logic circuit design

AU - Fuketa, Hiroshi

AU - Takahashi, Ryo

AU - Takamiya, Makoto

AU - Nomura, Masahiro

AU - Shinohara, Hirofumi

AU - Sakurai, Takayasu

PY - 2013

Y1 - 2013

N2 - Subthreshold logic circuits are one of promising solutions to achieve ultra-low power operation. However, subthreshold circuits are significantly sensitive to manufacturing and environmental variability. In this paper, we will discuss design challenges in subthreshold logic circuits, such as rise in a minimum operating voltage, signal integrity degradation, and large delay variations.

AB - Subthreshold logic circuits are one of promising solutions to achieve ultra-low power operation. However, subthreshold circuits are significantly sensitive to manufacturing and environmental variability. In this paper, we will discuss design challenges in subthreshold logic circuits, such as rise in a minimum operating voltage, signal integrity degradation, and large delay variations.

UR - http://www.scopus.com/inward/record.url?scp=84901325265&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84901325265&partnerID=8YFLogxK

U2 - 10.1109/ASICON.2013.6811842

DO - 10.1109/ASICON.2013.6811842

M3 - Conference contribution

AN - SCOPUS:84901325265

SN - 9781467364157

BT - Proceedings of International Conference on ASIC

PB - IEEE Computer Society

ER -