Variation-aware subthreshold logic circuit design

Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Subthreshold logic circuits are one of promising solutions to achieve ultra-low power operation. However, subthreshold circuits are significantly sensitive to manufacturing and environmental variability. In this paper, we will discuss design challenges in subthreshold logic circuits, such as rise in a minimum operating voltage, signal integrity degradation, and large delay variations.

Original languageEnglish
Title of host publication2013 IEEE 10th International Conference on ASIC, ASICON 2013
PublisherIEEE Computer Society
ISBN (Print)9781467364157
DOIs
Publication statusPublished - 2013 Jan 1
Externally publishedYes
Event2013 IEEE 10th International Conference on ASIC, ASICON 2013 - Shenzhen, China
Duration: 2013 Oct 282013 Oct 31

Publication series

NameProceedings of International Conference on ASIC
ISSN (Print)2162-7541
ISSN (Electronic)2162-755X

Other

Other2013 IEEE 10th International Conference on ASIC, ASICON 2013
CountryChina
CityShenzhen
Period13/10/2813/10/31

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Fuketa, H., Takahashi, R., Takamiya, M., Nomura, M., Shinohara, H., & Sakurai, T. (2013). Variation-aware subthreshold logic circuit design. In 2013 IEEE 10th International Conference on ASIC, ASICON 2013 [6811842] (Proceedings of International Conference on ASIC). IEEE Computer Society. https://doi.org/10.1109/ASICON.2013.6811842