Variation-aware subthreshold logic circuit design

Hiroshi Fuketa; Ryo Takahashi; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai

doi:10.1109/ASICON.2013.6811842

Variation-aware subthreshold logic circuit design

Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

Subthreshold logic circuits are one of promising solutions to achieve ultra-low power operation. However, subthreshold circuits are significantly sensitive to manufacturing and environmental variability. In this paper, we will discuss design challenges in subthreshold logic circuits, such as rise in a minimum operating voltage, signal integrity degradation, and large delay variations.

Original language	English
Title of host publication	Proceedings of International Conference on ASIC
Publisher	IEEE Computer Society
ISBN (Print)	9781467364157
DOIs	https://doi.org/10.1109/ASICON.2013.6811842
Publication status	Published - 2013
Externally published	Yes
Event	2013 IEEE 10th International Conference on ASIC, ASICON 2013 - Shenzhen, China Duration: 2013 Oct 28 → 2013 Oct 31

Other

Other	2013 IEEE 10th International Conference on ASIC, ASICON 2013
Country	China
City	Shenzhen
Period	13/10/28 → 13/10/31

Fingerprint

Logic design

Logic circuits

Degradation

Networks (circuits)

Electric potential

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Cite this

Fuketa, H., Takahashi, R., Takamiya, M., Nomura, M., Shinohara, H., & Sakurai, T. (2013). Variation-aware subthreshold logic circuit design. In Proceedings of International Conference on ASIC [6811842] IEEE Computer Society. https://doi.org/10.1109/ASICON.2013.6811842

Variation-aware subthreshold logic circuit design. / Fuketa, Hiroshi; Takahashi, Ryo; Takamiya, Makoto; Nomura, Masahiro; Shinohara, Hirofumi; Sakurai, Takayasu.

Proceedings of International Conference on ASIC. IEEE Computer Society, 2013. 6811842.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Fuketa, H, Takahashi, R, Takamiya, M, Nomura, M, Shinohara, H & Sakurai, T 2013, Variation-aware subthreshold logic circuit design. in Proceedings of International Conference on ASIC., 6811842, IEEE Computer Society, 2013 IEEE 10th International Conference on ASIC, ASICON 2013, Shenzhen, China, 13/10/28. https://doi.org/10.1109/ASICON.2013.6811842

Fuketa H, Takahashi R, Takamiya M, Nomura M, Shinohara H, Sakurai T. Variation-aware subthreshold logic circuit design. In Proceedings of International Conference on ASIC. IEEE Computer Society. 2013. 6811842 https://doi.org/10.1109/ASICON.2013.6811842

Fuketa, Hiroshi ; Takahashi, Ryo ; Takamiya, Makoto ; Nomura, Masahiro ; Shinohara, Hirofumi ; Sakurai, Takayasu. / Variation-aware subthreshold logic circuit design. Proceedings of International Conference on ASIC. IEEE Computer Society, 2013.

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Access to Document

10.1109/ASICON.2013.6811842