TY - GEN
T1 - Variation-aware subthreshold logic circuit design
AU - Fuketa, Hiroshi
AU - Takahashi, Ryo
AU - Takamiya, Makoto
AU - Nomura, Masahiro
AU - Shinohara, Hirofumi
AU - Sakurai, Takayasu
PY - 2013/1/1
Y1 - 2013/1/1
N2 - Subthreshold logic circuits are one of promising solutions to achieve ultra-low power operation. However, subthreshold circuits are significantly sensitive to manufacturing and environmental variability. In this paper, we will discuss design challenges in subthreshold logic circuits, such as rise in a minimum operating voltage, signal integrity degradation, and large delay variations.
AB - Subthreshold logic circuits are one of promising solutions to achieve ultra-low power operation. However, subthreshold circuits are significantly sensitive to manufacturing and environmental variability. In this paper, we will discuss design challenges in subthreshold logic circuits, such as rise in a minimum operating voltage, signal integrity degradation, and large delay variations.
UR - http://www.scopus.com/inward/record.url?scp=84901325265&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84901325265&partnerID=8YFLogxK
U2 - 10.1109/ASICON.2013.6811842
DO - 10.1109/ASICON.2013.6811842
M3 - Conference contribution
AN - SCOPUS:84901325265
SN - 9781467364157
T3 - Proceedings of International Conference on ASIC
BT - 2013 IEEE 10th International Conference on ASIC, ASICON 2013
PB - IEEE Computer Society
T2 - 2013 IEEE 10th International Conference on ASIC, ASICON 2013
Y2 - 28 October 2013 through 31 October 2013
ER -