VECTOR LABELLING METHOD IN FIXED POINTS ALGORITHM AND ARRAY PROCESSORS.

Shinichi Oishi, Tadaaki Takase, Kiyotaka Yamamura

    Research output: Contribution to journalArticle

    Abstract

    In this paper it is shown that the vector labeling algorithm, one of the typical fixed point algorithms, can be performed efficiently in parallel on a suitable array processor system. Under certain conditions, the time complexity of the vector labeling algorithm is determined by pivot operations. To further speed up the algorithm, a method is also shown for evading matrix inversion formerly needed at the beginning of the vector labeling algorithm.

    Original languageEnglish
    Pages (from-to)51-59
    Number of pages9
    JournalElectronics & communications in Japan
    Volume66
    Issue number11
    Publication statusPublished - 1983 Nov

    Fingerprint

    Parallel processing systems
    Labeling

    ASJC Scopus subject areas

    • Engineering(all)

    Cite this

    VECTOR LABELLING METHOD IN FIXED POINTS ALGORITHM AND ARRAY PROCESSORS. / Oishi, Shinichi; Takase, Tadaaki; Yamamura, Kiyotaka.

    In: Electronics & communications in Japan, Vol. 66, No. 11, 11.1983, p. 51-59.

    Research output: Contribution to journalArticle

    Oishi, Shinichi ; Takase, Tadaaki ; Yamamura, Kiyotaka. / VECTOR LABELLING METHOD IN FIXED POINTS ALGORITHM AND ARRAY PROCESSORS. In: Electronics & communications in Japan. 1983 ; Vol. 66, No. 11. pp. 51-59.
    @article{da93bb0f0f7d4097b962d1ea25d5a695,
    title = "VECTOR LABELLING METHOD IN FIXED POINTS ALGORITHM AND ARRAY PROCESSORS.",
    abstract = "In this paper it is shown that the vector labeling algorithm, one of the typical fixed point algorithms, can be performed efficiently in parallel on a suitable array processor system. Under certain conditions, the time complexity of the vector labeling algorithm is determined by pivot operations. To further speed up the algorithm, a method is also shown for evading matrix inversion formerly needed at the beginning of the vector labeling algorithm.",
    author = "Shinichi Oishi and Tadaaki Takase and Kiyotaka Yamamura",
    year = "1983",
    month = "11",
    language = "English",
    volume = "66",
    pages = "51--59",
    journal = "Electronics and Communications in Japan",
    issn = "0424-8368",
    publisher = "Scripta Pub Co.",
    number = "11",

    }

    TY - JOUR

    T1 - VECTOR LABELLING METHOD IN FIXED POINTS ALGORITHM AND ARRAY PROCESSORS.

    AU - Oishi, Shinichi

    AU - Takase, Tadaaki

    AU - Yamamura, Kiyotaka

    PY - 1983/11

    Y1 - 1983/11

    N2 - In this paper it is shown that the vector labeling algorithm, one of the typical fixed point algorithms, can be performed efficiently in parallel on a suitable array processor system. Under certain conditions, the time complexity of the vector labeling algorithm is determined by pivot operations. To further speed up the algorithm, a method is also shown for evading matrix inversion formerly needed at the beginning of the vector labeling algorithm.

    AB - In this paper it is shown that the vector labeling algorithm, one of the typical fixed point algorithms, can be performed efficiently in parallel on a suitable array processor system. Under certain conditions, the time complexity of the vector labeling algorithm is determined by pivot operations. To further speed up the algorithm, a method is also shown for evading matrix inversion formerly needed at the beginning of the vector labeling algorithm.

    UR - http://www.scopus.com/inward/record.url?scp=0020849743&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=0020849743&partnerID=8YFLogxK

    M3 - Article

    VL - 66

    SP - 51

    EP - 59

    JO - Electronics and Communications in Japan

    JF - Electronics and Communications in Japan

    SN - 0424-8368

    IS - 11

    ER -