In systems where the same data are distributed in plural memories, it is important for designers to verify that error recovery procedures maintain data consistency after a failure. A modeling and validation method of error recovery specifications by using colored Petri nets is proposed. The analysis of reachable states is useful to verify consistency. The introduction of the equivalence relation into reachable states reduces the number of the states to be verified. The proposed approach was applied to read/write control of a disk controller with a built-in cache memory.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 1991 Dec 1|
|Event||1991 IEEE International Symposium on Circuits and Systems Part 4 (of 5) - Singapore, Singapore|
Duration: 1991 Jun 11 → 1991 Jun 14
ASJC Scopus subject areas
- Electrical and Electronic Engineering