A system for quick VLSI architecture evaluation is proposed. It consists of a simple hardware description language, a simulator, and a synthesizer. The authors claim that by using this system, the designer can make sure of his architecture's design adequacy in a very short time.
|Title of host publication||Unknown Host Publication Title|
|Place of Publication||New York, NY, USA|
|Number of pages||4|
|Publication status||Published - 1986|
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