VLSI ARCHITECTURE EVALUATION SYSTEM.

Ryuichi Takahashi, Takeshi Yoshimura, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A system for quick VLSI architecture evaluation is proposed. It consists of a simple hardware description language, a simulator, and a synthesizer. The authors claim that by using this system, the designer can make sure of his architecture's design adequacy in a very short time.

Original languageEnglish
Title of host publicationUnknown Host Publication Title
Place of PublicationNew York, NY, USA
PublisherIEEE
Pages60-63
Number of pages4
ISBN (Print)0818607351
Publication statusPublished - 1986
Externally publishedYes

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Takahashi, R., Yoshimura, T., & Goto, S. (1986). VLSI ARCHITECTURE EVALUATION SYSTEM. In Unknown Host Publication Title (pp. 60-63). IEEE.