VLSI architecture for variable block size motion estimation in H.264/AVC with low cost memory organization

Yang Song, Zhenyu Liu, Takeshi Ikenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

A 1-D full search variable block sizes motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the add operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is required to store the search area and then reduces 72.7% hardware cost of SRAM. The design is realized with TSMC 0.18μm 1P6M technology with a hardware cost of 67.6K gates. In typical working condition (1.8V, 25°C), a clock frequency of 266MHz can be achieved.

Original languageEnglish
Title of host publication2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers
Pages89-92
Number of pages4
DOIs
Publication statusPublished - 2007
Event2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Hsinchu
Duration: 2007 Apr 262007 Apr 28

Other

Other2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006
CityHsinchu
Period07/4/2607/4/28

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Song, Y., Liu, Z., Ikenaga, T., & Goto, S. (2007). VLSI architecture for variable block size motion estimation in H.264/AVC with low cost memory organization. In 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers (pp. 89-92). [4027503] https://doi.org/10.1109/VDAT.2006.258131