VLSI architecture of a low complexity face detection algorithm for real-time video encoding

Tianruo Zhang, Minghui Wang, Chen Liu, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Combining video encoder and content analyzer to improve the encoding efficiency by content-aware algorithms is very challenging now. For the aiming application of low cost hardware real-time encoder with face detectionfor videophone, this paper proposes a face detection algorithm to detect each macroblock (MB) as one part of a face or not. This face detection algorithm has a unique estimation-and-verification process and can be combined with a H264 encoder by MB level pipeline architecture. 97.91% MBs in faces can be detected. VLSl architecture of proposed face detection algorithm is designed and an area of 4.3k gates is achieved. Power consumption is only 1.45mW at 100MHz. The detection speed achieves 1315fps in ClF sequences.

Original languageEnglish
Title of host publicationASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC
Pages147-150
Number of pages4
DOIs
Publication statusPublished - 2009
Event2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha
Duration: 2009 Oct 202009 Oct 23

Other

Other2009 8th IEEE International Conference on ASIC, ASICON 2009
CityChangsha
Period09/10/2009/10/23

Keywords

  • Face detection
  • VLSI architecture

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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