VLSI architecture of a low complexity face detection algorithm for real-time video encoding

Tianruo Zhang, Minghui Wang, Chen Liu, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Combining video encoder and content analyzer to improve the encoding efficiency by content-aware algorithms is very challenging now. For the aiming application of low cost hardware real-time encoder with face detectionfor videophone, this paper proposes a face detection algorithm to detect each macroblock (MB) as one part of a face or not. This face detection algorithm has a unique estimation-and-verification process and can be combined with a H264 encoder by MB level pipeline architecture. 97.91% MBs in faces can be detected. VLSl architecture of proposed face detection algorithm is designed and an area of 4.3k gates is achieved. Power consumption is only 1.45mW at 100MHz. The detection speed achieves 1315fps in ClF sequences.

Original languageEnglish
Title of host publicationASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC
Pages147-150
Number of pages4
DOIs
Publication statusPublished - 2009
Event2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha
Duration: 2009 Oct 202009 Oct 23

Other

Other2009 8th IEEE International Conference on ASIC, ASICON 2009
CityChangsha
Period09/10/2009/10/23

Fingerprint

Face recognition
Electric power utilization
Pipelines
Hardware
Costs

Keywords

  • Face detection
  • VLSI architecture

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Zhang, T., Wang, M., Liu, C., & Goto, S. (2009). VLSI architecture of a low complexity face detection algorithm for real-time video encoding. In ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC (pp. 147-150). [5351587] https://doi.org/10.1109/ASICON.2009.5351587

VLSI architecture of a low complexity face detection algorithm for real-time video encoding. / Zhang, Tianruo; Wang, Minghui; Liu, Chen; Goto, Satoshi.

ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC. 2009. p. 147-150 5351587.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zhang, T, Wang, M, Liu, C & Goto, S 2009, VLSI architecture of a low complexity face detection algorithm for real-time video encoding. in ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC., 5351587, pp. 147-150, 2009 8th IEEE International Conference on ASIC, ASICON 2009, Changsha, 09/10/20. https://doi.org/10.1109/ASICON.2009.5351587
Zhang T, Wang M, Liu C, Goto S. VLSI architecture of a low complexity face detection algorithm for real-time video encoding. In ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC. 2009. p. 147-150. 5351587 https://doi.org/10.1109/ASICON.2009.5351587
Zhang, Tianruo ; Wang, Minghui ; Liu, Chen ; Goto, Satoshi. / VLSI architecture of a low complexity face detection algorithm for real-time video encoding. ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC. 2009. pp. 147-150
@inproceedings{134259763c4e4e66bb2a953992dff05a,
title = "VLSI architecture of a low complexity face detection algorithm for real-time video encoding",
abstract = "Combining video encoder and content analyzer to improve the encoding efficiency by content-aware algorithms is very challenging now. For the aiming application of low cost hardware real-time encoder with face detectionfor videophone, this paper proposes a face detection algorithm to detect each macroblock (MB) as one part of a face or not. This face detection algorithm has a unique estimation-and-verification process and can be combined with a H264 encoder by MB level pipeline architecture. 97.91{\%} MBs in faces can be detected. VLSl architecture of proposed face detection algorithm is designed and an area of 4.3k gates is achieved. Power consumption is only 1.45mW at 100MHz. The detection speed achieves 1315fps in ClF sequences.",
keywords = "Face detection, VLSI architecture",
author = "Tianruo Zhang and Minghui Wang and Chen Liu and Satoshi Goto",
year = "2009",
doi = "10.1109/ASICON.2009.5351587",
language = "English",
isbn = "9781424438686",
pages = "147--150",
booktitle = "ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC",

}

TY - GEN

T1 - VLSI architecture of a low complexity face detection algorithm for real-time video encoding

AU - Zhang, Tianruo

AU - Wang, Minghui

AU - Liu, Chen

AU - Goto, Satoshi

PY - 2009

Y1 - 2009

N2 - Combining video encoder and content analyzer to improve the encoding efficiency by content-aware algorithms is very challenging now. For the aiming application of low cost hardware real-time encoder with face detectionfor videophone, this paper proposes a face detection algorithm to detect each macroblock (MB) as one part of a face or not. This face detection algorithm has a unique estimation-and-verification process and can be combined with a H264 encoder by MB level pipeline architecture. 97.91% MBs in faces can be detected. VLSl architecture of proposed face detection algorithm is designed and an area of 4.3k gates is achieved. Power consumption is only 1.45mW at 100MHz. The detection speed achieves 1315fps in ClF sequences.

AB - Combining video encoder and content analyzer to improve the encoding efficiency by content-aware algorithms is very challenging now. For the aiming application of low cost hardware real-time encoder with face detectionfor videophone, this paper proposes a face detection algorithm to detect each macroblock (MB) as one part of a face or not. This face detection algorithm has a unique estimation-and-verification process and can be combined with a H264 encoder by MB level pipeline architecture. 97.91% MBs in faces can be detected. VLSl architecture of proposed face detection algorithm is designed and an area of 4.3k gates is achieved. Power consumption is only 1.45mW at 100MHz. The detection speed achieves 1315fps in ClF sequences.

KW - Face detection

KW - VLSI architecture

UR - http://www.scopus.com/inward/record.url?scp=77949366410&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77949366410&partnerID=8YFLogxK

U2 - 10.1109/ASICON.2009.5351587

DO - 10.1109/ASICON.2009.5351587

M3 - Conference contribution

AN - SCOPUS:77949366410

SN - 9781424438686

SP - 147

EP - 150

BT - ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

ER -