VLSI chip set for a small mainframe processor.

S. Yamada, T. Sano, M. Saito, M. Motohashi, H. Oki, H. Tsuruya

Research output: Contribution to journalConference article

1 Citation (Scopus)

Abstract

A CMOS VLSI chip set, which consists of three chips including a chip with 495,000 transistors, 0.8-ns gate delay, and a 12-ns RAM, has been developed to achieve a high-performance 32-bit mainframe processor. This chip set uses a 1.2-μm double-diffused-drain transistor, double-layer metallization technology and a sophisticated CAD (computer-aided design) system. Each chip is mounted on a 288-pin surface-mount pin grid array package. A one-board CPU can be realized by assembling the chip set on a multilayer printed wiring board with RAMs and interface LSIs.

Original languageEnglish
Pages (from-to)24.6/1-4
JournalProceedings of the Custom Integrated Circuits Conference
Publication statusPublished - 1988 Dec 1
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Yamada, S., Sano, T., Saito, M., Motohashi, M., Oki, H., & Tsuruya, H. (1988). VLSI chip set for a small mainframe processor. Proceedings of the Custom Integrated Circuits Conference, 24.6/1-4.