VLSI friendly computation reduction scheme in H.264/AVC motion estimation

Yiqing Huang, Satoshi Goto, Takeshi Ikenaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In H.264/AVC standard, motion estimation (ME) can be executed on multiple reference frame (MRF) to improve the coding performance. For real-time hardwired encoder, the huge throughput of fractional motion estimation (FME) and integer motion estimation (IME) makes pipeline stage a must. So, IME is arranged in a single stage, which deteriorates the efficiency of many fast ME algorithms. This paper provides a VLSI friendly complexity reduction solution for ME procedure. Firstly, the proposed algorithm examines the pixel difference of current macroblock (MB) and adjust the available reference frame number. Secondly, it executes matching analysis to detect MB with static feature and early terminate the IME process. Thirdly, based on motion feature analysis result, the search range for non static MB is also adjusted and redundant search positions are eliminated. Compared with full search algorithm, the proposed fast ME algorithm can reduce 47.91% to 91.88% ME time with negligible video quality degradation. Furthermore, the algorithm can also be combined with other fast block matching process and friendly to hardwired encoder.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Pages844-847
Number of pages4
DOIs
Publication statusPublished - 2008
Event2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA
Duration: 2008 May 182008 May 21

Other

Other2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
CitySeattle, WA
Period08/5/1808/5/21

Fingerprint

Motion estimation
Pipelines
Pixels
Throughput
Degradation

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Huang, Y., Goto, S., & Ikenaga, T. (2008). VLSI friendly computation reduction scheme in H.264/AVC motion estimation. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 844-847). [4541550] https://doi.org/10.1109/ISCAS.2008.4541550

VLSI friendly computation reduction scheme in H.264/AVC motion estimation. / Huang, Yiqing; Goto, Satoshi; Ikenaga, Takeshi.

Proceedings - IEEE International Symposium on Circuits and Systems. 2008. p. 844-847 4541550.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Huang, Y, Goto, S & Ikenaga, T 2008, VLSI friendly computation reduction scheme in H.264/AVC motion estimation. in Proceedings - IEEE International Symposium on Circuits and Systems., 4541550, pp. 844-847, 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008, Seattle, WA, 08/5/18. https://doi.org/10.1109/ISCAS.2008.4541550
Huang Y, Goto S, Ikenaga T. VLSI friendly computation reduction scheme in H.264/AVC motion estimation. In Proceedings - IEEE International Symposium on Circuits and Systems. 2008. p. 844-847. 4541550 https://doi.org/10.1109/ISCAS.2008.4541550
Huang, Yiqing ; Goto, Satoshi ; Ikenaga, Takeshi. / VLSI friendly computation reduction scheme in H.264/AVC motion estimation. Proceedings - IEEE International Symposium on Circuits and Systems. 2008. pp. 844-847
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