VLSI implementation of HEVC motion compensation with distance biased direct cache mapping for 8K UHDTV applications

Shihao Wang, Dajiang Zhou, Jianbin Zhou, Takeshi Yoshimura, Satoshi Goto

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

Ultrahigh definition television is becoming increasingly attractive and practical with the doubled compression performance delivered by High Efficiency Video Coding (H.265/HEVC). Meanwhile, implementation of real-time video codecs is challenged by not only the huge throughput and memory bandwidth requirements but also the increased complexity of new algorithms. For motion compensation (MC) that is a known bottleneck in video decoding, the enlarged and diversified prediction unit sizes impose notably higher difficulties in trading off area, power, and memory traffic. This paper presents a very large scale integration implementation of HEVC MC that supports 7680 × 4320@60 frames/s bidirectional prediction. The MC design incorporates a highly efficient cache realized by novel architecture optimizations including distance biased directing mapping, eight-bank memory structure, row-based miss information compression, and mask-based block conflict checking. As a result, the proposed design not only achieves 8× throughput enhancement but also improves hardware efficiency by at least 2.01 times, in comparison with prior arts.

Original languageEnglish
Pages (from-to)380-393
Number of pages14
JournalIEEE Transactions on Circuits and Systems for Video Technology
Volume27
Issue number2
DOIs
Publication statusPublished - 2017 Feb 1

Fingerprint

Motion compensation
Data storage equipment
Throughput
VLSI circuits
Television
Image coding
Decoding
Masks
Hardware
Bandwidth

Keywords

  • Cache
  • H.264
  • H.265
  • High Efficiency Video Coding (HEVC)
  • interpolation
  • motion compensation (MC)
  • ultrahigh definition television (UHDTV)
  • very large scale integration (VLSI)
  • video decoder

ASJC Scopus subject areas

  • Media Technology
  • Electrical and Electronic Engineering

Cite this

VLSI implementation of HEVC motion compensation with distance biased direct cache mapping for 8K UHDTV applications. / Wang, Shihao; Zhou, Dajiang; Zhou, Jianbin; Yoshimura, Takeshi; Goto, Satoshi.

In: IEEE Transactions on Circuits and Systems for Video Technology, Vol. 27, No. 2, 01.02.2017, p. 380-393.

Research output: Contribution to journalArticle

Wang, Shihao ; Zhou, Dajiang ; Zhou, Jianbin ; Yoshimura, Takeshi ; Goto, Satoshi. / VLSI implementation of HEVC motion compensation with distance biased direct cache mapping for 8K UHDTV applications. In: IEEE Transactions on Circuits and Systems for Video Technology. 2017 ; Vol. 27, No. 2. pp. 380-393.
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