### Abstract

In H.264/AVC standard, motion estimation can be processed on multiple reference frames (MRF) to improve the video coding performance. For the VLSI real-time encoder, the heavy computation of fractional motion estimation (FME) makes the integer motion estimation (IME) and FME must be scheduled in two macro block (MB) pipeline stages, which makes many fast MRF algorithms inefficient for the computation reduction. In this paper, two algorithms are provided to reduce the computation of FME and IME. First, through analyzing the block's Hadamard transform coefficients, all-zero case after quantization can be accurately detected. The FME processing in the remaining frames for the block, detected as all-zero one, can be eliminated. Second, because the fast motion object blurs its edges in image, the effect of MRF to aliasing is weakened. The first reference frame is enough for fast motion MBs and MRF is just processed on those slow motion MBs with a small search range. The computation of IME is also highly reduced with this algorithm. Experimental results show that 61.4%-76.7% computation can be saved with the similar coding quality as the reference software. Moreover, the provided fast algorithms can be combined with fast block matching algorithms to further improve the performance.

Original language | English |
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Title of host publication | Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007 |

Pages | 1902-1905 |

Number of pages | 4 |

Publication status | Published - 2007 |

Event | IEEE International Conference onMultimedia and Expo, ICME 2007 - Beijing Duration: 2007 Jul 2 → 2007 Jul 5 |

### Other

Other | IEEE International Conference onMultimedia and Expo, ICME 2007 |
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City | Beijing |

Period | 07/7/2 → 07/7/5 |

### Fingerprint

### ASJC Scopus subject areas

- Computer Graphics and Computer-Aided Design
- Software

### Cite this

*Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007*(pp. 1902-1905). [4285047]

**VLSI oriented fast multiple reference frame motion estimation algorithm for H.264/AVC.** / Liu, Zhenyu; Li, Ngfeng; Song, Yang; Ikenaga, Takeshi; Goto, Satoshi.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

*Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007.*, 4285047, pp. 1902-1905, IEEE International Conference onMultimedia and Expo, ICME 2007, Beijing, 07/7/2.

}

TY - GEN

T1 - VLSI oriented fast multiple reference frame motion estimation algorithm for H.264/AVC

AU - Liu, Zhenyu

AU - Li, Ngfeng

AU - Song, Yang

AU - Ikenaga, Takeshi

AU - Goto, Satoshi

PY - 2007

Y1 - 2007

N2 - In H.264/AVC standard, motion estimation can be processed on multiple reference frames (MRF) to improve the video coding performance. For the VLSI real-time encoder, the heavy computation of fractional motion estimation (FME) makes the integer motion estimation (IME) and FME must be scheduled in two macro block (MB) pipeline stages, which makes many fast MRF algorithms inefficient for the computation reduction. In this paper, two algorithms are provided to reduce the computation of FME and IME. First, through analyzing the block's Hadamard transform coefficients, all-zero case after quantization can be accurately detected. The FME processing in the remaining frames for the block, detected as all-zero one, can be eliminated. Second, because the fast motion object blurs its edges in image, the effect of MRF to aliasing is weakened. The first reference frame is enough for fast motion MBs and MRF is just processed on those slow motion MBs with a small search range. The computation of IME is also highly reduced with this algorithm. Experimental results show that 61.4%-76.7% computation can be saved with the similar coding quality as the reference software. Moreover, the provided fast algorithms can be combined with fast block matching algorithms to further improve the performance.

AB - In H.264/AVC standard, motion estimation can be processed on multiple reference frames (MRF) to improve the video coding performance. For the VLSI real-time encoder, the heavy computation of fractional motion estimation (FME) makes the integer motion estimation (IME) and FME must be scheduled in two macro block (MB) pipeline stages, which makes many fast MRF algorithms inefficient for the computation reduction. In this paper, two algorithms are provided to reduce the computation of FME and IME. First, through analyzing the block's Hadamard transform coefficients, all-zero case after quantization can be accurately detected. The FME processing in the remaining frames for the block, detected as all-zero one, can be eliminated. Second, because the fast motion object blurs its edges in image, the effect of MRF to aliasing is weakened. The first reference frame is enough for fast motion MBs and MRF is just processed on those slow motion MBs with a small search range. The computation of IME is also highly reduced with this algorithm. Experimental results show that 61.4%-76.7% computation can be saved with the similar coding quality as the reference software. Moreover, the provided fast algorithms can be combined with fast block matching algorithms to further improve the performance.

UR - http://www.scopus.com/inward/record.url?scp=46449088525&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=46449088525&partnerID=8YFLogxK

M3 - Conference contribution

SN - 1424410177

SN - 9781424410170

SP - 1902

EP - 1905

BT - Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007

ER -