Voltage island-driven power optimization for application specific network-on-chip design

Kan Wang, Sheqin Dong, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

In this paper, a voltage island aware framework is proposed for low power design of application specific NoC (LPASNoC). Through a three-phase processing including voltage island generation, VI-driven floorplanning and post-floorplan processing, the total power consumption, design cost and total wire length can be optimized. Experimental results show that compared to traditional ASNoC, the proposed method can reduce total core power by about 34.5% and chip area by about 26.8% without increasing communication power.

Original languageEnglish
Title of host publicationProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Pages171-176
Number of pages6
DOIs
Publication statusPublished - 2012
Event22nd Great Lakes Symposium on VLSI, GLSVLSI'2012 - Salt Lake City, UT
Duration: 2012 May 32012 May 4

Other

Other22nd Great Lakes Symposium on VLSI, GLSVLSI'2012
CitySalt Lake City, UT
Period12/5/312/5/4

Fingerprint

Electric potential
Processing
Electric power utilization
Wire
Communication
Costs
Network-on-chip

Keywords

  • Application specific NoC
  • Multiple supply voltages
  • Network components
  • Power consumption
  • Voltage island

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Wang, K., Dong, S., & Goto, S. (2012). Voltage island-driven power optimization for application specific network-on-chip design. In Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI (pp. 171-176) https://doi.org/10.1145/2206781.2206823

Voltage island-driven power optimization for application specific network-on-chip design. / Wang, Kan; Dong, Sheqin; Goto, Satoshi.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. 2012. p. 171-176.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wang, K, Dong, S & Goto, S 2012, Voltage island-driven power optimization for application specific network-on-chip design. in Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. pp. 171-176, 22nd Great Lakes Symposium on VLSI, GLSVLSI'2012, Salt Lake City, UT, 12/5/3. https://doi.org/10.1145/2206781.2206823
Wang K, Dong S, Goto S. Voltage island-driven power optimization for application specific network-on-chip design. In Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. 2012. p. 171-176 https://doi.org/10.1145/2206781.2206823
Wang, Kan ; Dong, Sheqin ; Goto, Satoshi. / Voltage island-driven power optimization for application specific network-on-chip design. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. 2012. pp. 171-176
@inproceedings{2a784abbdbca4dbcb2925ff74cd0661c,
title = "Voltage island-driven power optimization for application specific network-on-chip design",
abstract = "In this paper, a voltage island aware framework is proposed for low power design of application specific NoC (LPASNoC). Through a three-phase processing including voltage island generation, VI-driven floorplanning and post-floorplan processing, the total power consumption, design cost and total wire length can be optimized. Experimental results show that compared to traditional ASNoC, the proposed method can reduce total core power by about 34.5{\%} and chip area by about 26.8{\%} without increasing communication power.",
keywords = "Application specific NoC, Multiple supply voltages, Network components, Power consumption, Voltage island",
author = "Kan Wang and Sheqin Dong and Satoshi Goto",
year = "2012",
doi = "10.1145/2206781.2206823",
language = "English",
isbn = "9781450312448",
pages = "171--176",
booktitle = "Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI",

}

TY - GEN

T1 - Voltage island-driven power optimization for application specific network-on-chip design

AU - Wang, Kan

AU - Dong, Sheqin

AU - Goto, Satoshi

PY - 2012

Y1 - 2012

N2 - In this paper, a voltage island aware framework is proposed for low power design of application specific NoC (LPASNoC). Through a three-phase processing including voltage island generation, VI-driven floorplanning and post-floorplan processing, the total power consumption, design cost and total wire length can be optimized. Experimental results show that compared to traditional ASNoC, the proposed method can reduce total core power by about 34.5% and chip area by about 26.8% without increasing communication power.

AB - In this paper, a voltage island aware framework is proposed for low power design of application specific NoC (LPASNoC). Through a three-phase processing including voltage island generation, VI-driven floorplanning and post-floorplan processing, the total power consumption, design cost and total wire length can be optimized. Experimental results show that compared to traditional ASNoC, the proposed method can reduce total core power by about 34.5% and chip area by about 26.8% without increasing communication power.

KW - Application specific NoC

KW - Multiple supply voltages

KW - Network components

KW - Power consumption

KW - Voltage island

UR - http://www.scopus.com/inward/record.url?scp=84861123143&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84861123143&partnerID=8YFLogxK

U2 - 10.1145/2206781.2206823

DO - 10.1145/2206781.2206823

M3 - Conference contribution

SN - 9781450312448

SP - 171

EP - 176

BT - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

ER -