Voltage island-driven power optimization for application specific network-on-chip design

Kan Wang; Sheqin Dong; Satoshi Goto

doi:10.1145/2206781.2206823

Voltage island-driven power optimization for application specific network-on-chip design

Kan Wang, Sheqin Dong, Satoshi Goto

Waseda University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

In this paper, a voltage island aware framework is proposed for low power design of application specific NoC (LPASNoC). Through a three-phase processing including voltage island generation, VI-driven floorplanning and post-floorplan processing, the total power consumption, design cost and total wire length can be optimized. Experimental results show that compared to traditional ASNoC, the proposed method can reduce total core power by about 34.5% and chip area by about 26.8% without increasing communication power.

Original language	English
Title of host publication	Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Pages	171-176
Number of pages	6
DOIs	https://doi.org/10.1145/2206781.2206823
Publication status	Published - 2012
Event	22nd Great Lakes Symposium on VLSI, GLSVLSI'2012 - Salt Lake City, UT Duration: 2012 May 3 → 2012 May 4

Other

Other	22nd Great Lakes Symposium on VLSI, GLSVLSI'2012
City	Salt Lake City, UT
Period	12/5/3 → 12/5/4

Keywords

Application specific NoC
Multiple supply voltages
Network components
Power consumption
Voltage island

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1145/2206781.2206823

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Cite this

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title = "Voltage island-driven power optimization for application specific network-on-chip design",

abstract = "In this paper, a voltage island aware framework is proposed for low power design of application specific NoC (LPASNoC). Through a three-phase processing including voltage island generation, VI-driven floorplanning and post-floorplan processing, the total power consumption, design cost and total wire length can be optimized. Experimental results show that compared to traditional ASNoC, the proposed method can reduce total core power by about 34.5% and chip area by about 26.8% without increasing communication power.",

keywords = "Application specific NoC, Multiple supply voltages, Network components, Power consumption, Voltage island",

author = "Kan Wang and Sheqin Dong and Satoshi Goto",

year = "2012",

doi = "10.1145/2206781.2206823",

language = "English",

isbn = "9781450312448",

pages = "171--176",

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note = "22nd Great Lakes Symposium on VLSI, GLSVLSI'2012 ; Conference date: 03-05-2012 Through 04-05-2012",

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AU - Wang, Kan

AU - Dong, Sheqin

AU - Goto, Satoshi

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N2 - In this paper, a voltage island aware framework is proposed for low power design of application specific NoC (LPASNoC). Through a three-phase processing including voltage island generation, VI-driven floorplanning and post-floorplan processing, the total power consumption, design cost and total wire length can be optimized. Experimental results show that compared to traditional ASNoC, the proposed method can reduce total core power by about 34.5% and chip area by about 26.8% without increasing communication power.

AB - In this paper, a voltage island aware framework is proposed for low power design of application specific NoC (LPASNoC). Through a three-phase processing including voltage island generation, VI-driven floorplanning and post-floorplan processing, the total power consumption, design cost and total wire length can be optimized. Experimental results show that compared to traditional ASNoC, the proposed method can reduce total core power by about 34.5% and chip area by about 26.8% without increasing communication power.

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KW - Multiple supply voltages

KW - Network components

KW - Power consumption

KW - Voltage island

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BT - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

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