Voltage island-driven power optimization for application specific network-on-chip design

Kan Wang, Sheqin Dong, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

In this paper, a voltage island aware framework is proposed for low power design of application specific NoC (LPASNoC). Through a three-phase processing including voltage island generation, VI-driven floorplanning and post-floorplan processing, the total power consumption, design cost and total wire length can be optimized. Experimental results show that compared to traditional ASNoC, the proposed method can reduce total core power by about 34.5% and chip area by about 26.8% without increasing communication power.

Original languageEnglish
Title of host publicationProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Pages171-176
Number of pages6
DOIs
Publication statusPublished - 2012
Event22nd Great Lakes Symposium on VLSI, GLSVLSI'2012 - Salt Lake City, UT
Duration: 2012 May 32012 May 4

Other

Other22nd Great Lakes Symposium on VLSI, GLSVLSI'2012
CitySalt Lake City, UT
Period12/5/312/5/4

Keywords

  • Application specific NoC
  • Multiple supply voltages
  • Network components
  • Power consumption
  • Voltage island

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Wang, K., Dong, S., & Goto, S. (2012). Voltage island-driven power optimization for application specific network-on-chip design. In Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI (pp. 171-176) https://doi.org/10.1145/2206781.2206823