Abstract
In this paper, a voltage island aware framework is proposed for low power design of application specific NoC (LPASNoC). Through a three-phase processing including voltage island generation, VI-driven floorplanning and post-floorplan processing, the total power consumption, design cost and total wire length can be optimized. Experimental results show that compared to traditional ASNoC, the proposed method can reduce total core power by about 34.5% and chip area by about 26.8% without increasing communication power.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI |
| Pages | 171-176 |
| Number of pages | 6 |
| DOIs | |
| Publication status | Published - 2012 |
| Event | 22nd Great Lakes Symposium on VLSI, GLSVLSI'2012 - Salt Lake City, UT Duration: 2012 May 3 → 2012 May 4 |
Other
| Other | 22nd Great Lakes Symposium on VLSI, GLSVLSI'2012 |
|---|---|
| City | Salt Lake City, UT |
| Period | 12/5/3 → 12/5/4 |
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Keywords
- Application specific NoC
- Multiple supply voltages
- Network components
- Power consumption
- Voltage island
ASJC Scopus subject areas
- Engineering(all)
Cite this
Voltage island-driven power optimization for application specific network-on-chip design. / Wang, Kan; Dong, Sheqin; Goto, Satoshi.
Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. 2012. p. 171-176.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Voltage island-driven power optimization for application specific network-on-chip design
AU - Wang, Kan
AU - Dong, Sheqin
AU - Goto, Satoshi
PY - 2012
Y1 - 2012
N2 - In this paper, a voltage island aware framework is proposed for low power design of application specific NoC (LPASNoC). Through a three-phase processing including voltage island generation, VI-driven floorplanning and post-floorplan processing, the total power consumption, design cost and total wire length can be optimized. Experimental results show that compared to traditional ASNoC, the proposed method can reduce total core power by about 34.5% and chip area by about 26.8% without increasing communication power.
AB - In this paper, a voltage island aware framework is proposed for low power design of application specific NoC (LPASNoC). Through a three-phase processing including voltage island generation, VI-driven floorplanning and post-floorplan processing, the total power consumption, design cost and total wire length can be optimized. Experimental results show that compared to traditional ASNoC, the proposed method can reduce total core power by about 34.5% and chip area by about 26.8% without increasing communication power.
KW - Application specific NoC
KW - Multiple supply voltages
KW - Network components
KW - Power consumption
KW - Voltage island
UR - http://www.scopus.com/inward/record.url?scp=84861123143&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84861123143&partnerID=8YFLogxK
U2 - 10.1145/2206781.2206823
DO - 10.1145/2206781.2206823
M3 - Conference contribution
AN - SCOPUS:84861123143
SN - 9781450312448
SP - 171
EP - 176
BT - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
ER -