Abstract
In this paper, a voltage island aware framework is proposed for low power design of application specific NoC (LPASNoC). Through a three-phase processing including voltage island generation, VI-driven floorplanning and post-floorplan processing, the total power consumption, design cost and total wire length can be optimized. Experimental results show that compared to traditional ASNoC, the proposed method can reduce total core power by about 34.5% and chip area by about 26.8% without increasing communication power.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI |
| Pages | 171-176 |
| Number of pages | 6 |
| DOIs | |
| Publication status | Published - 2012 |
| Event | 22nd Great Lakes Symposium on VLSI, GLSVLSI'2012 - Salt Lake City, UT Duration: 2012 May 3 → 2012 May 4 |
Other
| Other | 22nd Great Lakes Symposium on VLSI, GLSVLSI'2012 |
|---|---|
| City | Salt Lake City, UT |
| Period | 12/5/3 → 12/5/4 |
Keywords
- Application specific NoC
- Multiple supply voltages
- Network components
- Power consumption
- Voltage island
ASJC Scopus subject areas
- Engineering(all)
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Wang, K., Dong, S., & Goto, S. (2012). Voltage island-driven power optimization for application specific network-on-chip design. In Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI (pp. 171-176) https://doi.org/10.1145/2206781.2206823