Waiting false path analysis of sequential logic circuits for performance optimization

Kazuhiro Nakamura, Kazuyoshi Takagi, Shinji Kimura, Katsumasa Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

This paper introduces a new class of false path, which is sensitizable but does not affect the decision of the clock period. We call such false paths waiting false paths, which correspond to multi-cycle operations controlled by wait states. The allowable delay time of waiting false paths is greater than the clock period. When the number of allowable clock cycles for each path is determined, the delay of the path can be the product of the clock period and the allowable cycles. This paper presents a method to analyze allowable cycles and to detect waiting false paths based on symbolic traversal of FSM. We have applied our method to 30 ISCAS89 FSM benchmarks and found that 22 circuits include such paths. 11 circuits among them include such paths which are critical paths, where the delay is measured as the number of gates on the path. Information on such paths can be used in the logic synthesis to reduce the number of gates and in the layout synthesis to reduce the size of gates.

Original languageEnglish
Title of host publicationIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
EditorsH. Yasuura, J. White
PublisherIEEE Comp Soc
Pages392-395
Number of pages4
Publication statusPublished - 1998
Externally publishedYes
EventProceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD - San Jose, CA, USA
Duration: 1998 Nov 81998 Nov 12

Other

OtherProceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD
CitySan Jose, CA, USA
Period98/11/898/11/12

Fingerprint

Sequential circuits
Clocks
Networks (circuits)
Time delay

ASJC Scopus subject areas

  • Software

Cite this

Nakamura, K., Takagi, K., Kimura, S., & Watanabe, K. (1998). Waiting false path analysis of sequential logic circuits for performance optimization. In H. Yasuura, & J. White (Eds.), IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers (pp. 392-395). IEEE Comp Soc.

Waiting false path analysis of sequential logic circuits for performance optimization. / Nakamura, Kazuhiro; Takagi, Kazuyoshi; Kimura, Shinji; Watanabe, Katsumasa.

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. ed. / H. Yasuura; J. White. IEEE Comp Soc, 1998. p. 392-395.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nakamura, K, Takagi, K, Kimura, S & Watanabe, K 1998, Waiting false path analysis of sequential logic circuits for performance optimization. in H Yasuura & J White (eds), IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. IEEE Comp Soc, pp. 392-395, Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD, San Jose, CA, USA, 98/11/8.
Nakamura K, Takagi K, Kimura S, Watanabe K. Waiting false path analysis of sequential logic circuits for performance optimization. In Yasuura H, White J, editors, IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. IEEE Comp Soc. 1998. p. 392-395
Nakamura, Kazuhiro ; Takagi, Kazuyoshi ; Kimura, Shinji ; Watanabe, Katsumasa. / Waiting false path analysis of sequential logic circuits for performance optimization. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. editor / H. Yasuura ; J. White. IEEE Comp Soc, 1998. pp. 392-395
@inproceedings{e84d24dcd9a741f39d92e0376dd96a21,
title = "Waiting false path analysis of sequential logic circuits for performance optimization",
abstract = "This paper introduces a new class of false path, which is sensitizable but does not affect the decision of the clock period. We call such false paths waiting false paths, which correspond to multi-cycle operations controlled by wait states. The allowable delay time of waiting false paths is greater than the clock period. When the number of allowable clock cycles for each path is determined, the delay of the path can be the product of the clock period and the allowable cycles. This paper presents a method to analyze allowable cycles and to detect waiting false paths based on symbolic traversal of FSM. We have applied our method to 30 ISCAS89 FSM benchmarks and found that 22 circuits include such paths. 11 circuits among them include such paths which are critical paths, where the delay is measured as the number of gates on the path. Information on such paths can be used in the logic synthesis to reduce the number of gates and in the layout synthesis to reduce the size of gates.",
author = "Kazuhiro Nakamura and Kazuyoshi Takagi and Shinji Kimura and Katsumasa Watanabe",
year = "1998",
language = "English",
pages = "392--395",
editor = "H. Yasuura and J. White",
booktitle = "IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers",
publisher = "IEEE Comp Soc",

}

TY - GEN

T1 - Waiting false path analysis of sequential logic circuits for performance optimization

AU - Nakamura, Kazuhiro

AU - Takagi, Kazuyoshi

AU - Kimura, Shinji

AU - Watanabe, Katsumasa

PY - 1998

Y1 - 1998

N2 - This paper introduces a new class of false path, which is sensitizable but does not affect the decision of the clock period. We call such false paths waiting false paths, which correspond to multi-cycle operations controlled by wait states. The allowable delay time of waiting false paths is greater than the clock period. When the number of allowable clock cycles for each path is determined, the delay of the path can be the product of the clock period and the allowable cycles. This paper presents a method to analyze allowable cycles and to detect waiting false paths based on symbolic traversal of FSM. We have applied our method to 30 ISCAS89 FSM benchmarks and found that 22 circuits include such paths. 11 circuits among them include such paths which are critical paths, where the delay is measured as the number of gates on the path. Information on such paths can be used in the logic synthesis to reduce the number of gates and in the layout synthesis to reduce the size of gates.

AB - This paper introduces a new class of false path, which is sensitizable but does not affect the decision of the clock period. We call such false paths waiting false paths, which correspond to multi-cycle operations controlled by wait states. The allowable delay time of waiting false paths is greater than the clock period. When the number of allowable clock cycles for each path is determined, the delay of the path can be the product of the clock period and the allowable cycles. This paper presents a method to analyze allowable cycles and to detect waiting false paths based on symbolic traversal of FSM. We have applied our method to 30 ISCAS89 FSM benchmarks and found that 22 circuits include such paths. 11 circuits among them include such paths which are critical paths, where the delay is measured as the number of gates on the path. Information on such paths can be used in the logic synthesis to reduce the number of gates and in the layout synthesis to reduce the size of gates.

UR - http://www.scopus.com/inward/record.url?scp=0032318394&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032318394&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0032318394

SP - 392

EP - 395

BT - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

A2 - Yasuura, H.

A2 - White, J.

PB - IEEE Comp Soc

ER -