Weighted adders with selector logics for super-resolution and its FPGA-based evaluation

Hiromine Yoshihara, Masao Yanagisawa, Nozomu Togawa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Super-resolution is a technique to remove the noise of observed images and restore its high frequencies. We focus on reconstruction-based super-resolution. Reconstruction requires large computation cost since it requires many images. In this paper, we propose a fast weighted adder for reconstruction-based super-resolution. From the viewpoint of reducing partial products, we propose two approaches to speed up a weighted adder. First, we use selector logics to halve its partial products. Second, we propose a weights-range limit method utilizing negative term. By applying our proposed approaches to a weighted adder, we can reduce carry propagations and our weighted adder can be designed by a fast circuit as compared to conventional ones. Experimental evaluations demonstrate that our weighted adder improves the performance by a maximum of 29.9% and reduces a maximum of 592 LUTs, compared to conventional implementations.

Original languageEnglish
Title of host publication2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
Pages603-606
Number of pages4
DOIs
Publication statusPublished - 2012 Dec 1
Event2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012 - Kaohsiung, Taiwan, Province of China
Duration: 2012 Dec 22012 Dec 5

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

Conference2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
CountryTaiwan, Province of China
CityKaohsiung
Period12/12/212/12/5

Keywords

  • FPGA
  • partial product
  • selector logics
  • super-resolution
  • weighted adder

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Yoshihara, H., Yanagisawa, M., & Togawa, N. (2012). Weighted adders with selector logics for super-resolution and its FPGA-based evaluation. In 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012 (pp. 603-606). [6419107] (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2012.6419107