Weighted adders with selector logics for super-resolution and its FPGA-based evaluation

Hiromine Yoshihara, Masao Yanagisawa, Nozomu Togawa

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)

    Abstract

    Super-resolution is a technique to remove the noise of observed images and restore its high frequencies. We focus on reconstruction-based super-resolution. Reconstruction requires large computation cost since it requires many images. In this paper, we propose a fast weighted adder for reconstruction-based super-resolution. From the viewpoint of reducing partial products, we propose two approaches to speed up a weighted adder. First, we use selector logics to halve its partial products. Second, we propose a weights-range limit method utilizing negative term. By applying our proposed approaches to a weighted adder, we can reduce carry propagations and our weighted adder can be designed by a fast circuit as compared to conventional ones. Experimental evaluations demonstrate that our weighted adder improves the performance by a maximum of 29.9% and reduces a maximum of 592 LUTs, compared to conventional implementations.

    Original languageEnglish
    Title of host publicationIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
    Pages603-606
    Number of pages4
    DOIs
    Publication statusPublished - 2012
    Event2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012 - Kaohsiung
    Duration: 2012 Dec 22012 Dec 5

    Other

    Other2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
    CityKaohsiung
    Period12/12/212/12/5

    Fingerprint

    Adders
    Field programmable gate arrays (FPGA)
    Networks (circuits)
    Costs

    Keywords

    • FPGA
    • partial product
    • selector logics
    • super-resolution
    • weighted adder

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Yoshihara, H., Yanagisawa, M., & Togawa, N. (2012). Weighted adders with selector logics for super-resolution and its FPGA-based evaluation. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS (pp. 603-606). [6419107] https://doi.org/10.1109/APCCAS.2012.6419107

    Weighted adders with selector logics for super-resolution and its FPGA-based evaluation. / Yoshihara, Hiromine; Yanagisawa, Masao; Togawa, Nozomu.

    IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2012. p. 603-606 6419107.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Yoshihara, H, Yanagisawa, M & Togawa, N 2012, Weighted adders with selector logics for super-resolution and its FPGA-based evaluation. in IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS., 6419107, pp. 603-606, 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012, Kaohsiung, 12/12/2. https://doi.org/10.1109/APCCAS.2012.6419107
    Yoshihara H, Yanagisawa M, Togawa N. Weighted adders with selector logics for super-resolution and its FPGA-based evaluation. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2012. p. 603-606. 6419107 https://doi.org/10.1109/APCCAS.2012.6419107
    Yoshihara, Hiromine ; Yanagisawa, Masao ; Togawa, Nozomu. / Weighted adders with selector logics for super-resolution and its FPGA-based evaluation. IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2012. pp. 603-606
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