Whitespace insertion for through-silicon via planning on 3-D SoCs

Wei Zhong, Song Chen, Takeshi Yoshimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

As technology advances, 3-D ICs can significantly alleviate the interconnect problem coming with the decreasing of feature size and are promising for heterogeneous integration. In 3-D ICs, one of the key challenges is the vertical technology, using through-silicon via (TSV) for different device layers connection. In this paper, by noticing the TSV assignment comes under the influence of the whitespace distribution in a given 3-D floorplan, we proposed an algorithm called whitespace insertion (WSI) based on the floorplan-representation Sequence Pair to make the whitespace distribution in the given floorplan more reasonable for TSV insertion. When given 3-D circuit placement or floorplan results, we also proposed a minimum spanning tree based algorithm for TSV assignment to minimize the total wire length, assuming each net may have at most one TSV on each device layer. Experimental results show that, in the given 3-D floorplans there is a huge gap about 45.54% of the wire length increase between the ideal and the practice. And based on our method, the total wire length can be reduced by 13% on average without changing the chip area.

Original languageEnglish
Title of host publicationISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems
Pages913-916
Number of pages4
DOIs
Publication statusPublished - 2010
Event2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris
Duration: 2010 May 302010 Jun 2

Other

Other2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
CityParis
Period10/5/3010/6/2

Fingerprint

Planning
Silicon
Wire
Networks (circuits)
Three dimensional integrated circuits

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Zhong, W., Chen, S., & Yoshimura, T. (2010). Whitespace insertion for through-silicon via planning on 3-D SoCs. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp. 913-916). [5537404] https://doi.org/10.1109/ISCAS.2010.5537404

Whitespace insertion for through-silicon via planning on 3-D SoCs. / Zhong, Wei; Chen, Song; Yoshimura, Takeshi.

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 913-916 5537404.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zhong, W, Chen, S & Yoshimura, T 2010, Whitespace insertion for through-silicon via planning on 3-D SoCs. in ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5537404, pp. 913-916, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, 10/5/30. https://doi.org/10.1109/ISCAS.2010.5537404
Zhong W, Chen S, Yoshimura T. Whitespace insertion for through-silicon via planning on 3-D SoCs. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 913-916. 5537404 https://doi.org/10.1109/ISCAS.2010.5537404
Zhong, Wei ; Chen, Song ; Yoshimura, Takeshi. / Whitespace insertion for through-silicon via planning on 3-D SoCs. ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. pp. 913-916
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