Wide operational margin capability of 1 kbit spin-transfer-torque memory array chip with 1-PMOS and 1-bottom-pin-magnetic-tunnel-junction type cell

Hiroki Koike, Takashi Ohsawa, Sadahiko Miura, Hiroaki Honjo, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

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8 Citations (Scopus)


This paper discusses the optimal combination of 1 transistor (T) and 1 magnetic tunnel junction (MTJ) type cell for spin transfer torque memory. Taking into consideration of current magnitude for both the Tand the MTJ, either PMOS-bottom pin structure or NMOS-top pin structure can be a promising choice. Focusing on the PMOS-bottom pin structure from the viewpoint of avoiding process difficulty, we clarified the condition that the structure would be effective. In order to verify the structure's effectiveness, a stand-alone MTJ test element group and a 1 kbit memory array chip were designed and fabricated with 90nm CMOS/100nm MTJ process. With the pass bit percentage measurement of the memory chip, we successfully demonstrated that 1-PMOS and 1-bottom-pin-MTJ has the wide operation margin of 100% pass at near 1.6V. It will be an effective solution for 1T-1MTJ memories.

Original languageEnglish
Article number04ED13
JournalJapanese Journal of Applied Physics
Issue number4 SPEC. ISSUE
Publication statusPublished - 2014
Externally publishedYes


ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

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