Wide operational margin capability of 1 kbit spin-transfer-torque memory array chip with 1-PMOS and 1-bottom-pin-magnetic-tunnel-junction type cell

Hiroki Koike, Takashi Ohsawa, Sadahiko Miura, Hiroaki Honjo, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

This paper discusses the optimal combination of 1 transistor (T) and 1 magnetic tunnel junction (MTJ) type cell for spin transfer torque memory. Taking into consideration of current magnitude for both the Tand the MTJ, either PMOS-bottom pin structure or NMOS-top pin structure can be a promising choice. Focusing on the PMOS-bottom pin structure from the viewpoint of avoiding process difficulty, we clarified the condition that the structure would be effective. In order to verify the structure's effectiveness, a stand-alone MTJ test element group and a 1 kbit memory array chip were designed and fabricated with 90nm CMOS/100nm MTJ process. With the pass bit percentage measurement of the memory chip, we successfully demonstrated that 1-PMOS and 1-bottom-pin-MTJ has the wide operation margin of 100% pass at near 1.6V. It will be an effective solution for 1T-1MTJ memories.

Original languageEnglish
Article number04ED13
JournalJapanese Journal of Applied Physics
Volume53
Issue number4 SPEC. ISSUE
DOIs
Publication statusPublished - 2014
Externally publishedYes

Fingerprint

Tunnel junctions
tunnel junctions
torque
margins
Torque
chips
Data storage equipment
cells
CMOS
Transistors
transistors

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

Cite this

Wide operational margin capability of 1 kbit spin-transfer-torque memory array chip with 1-PMOS and 1-bottom-pin-magnetic-tunnel-junction type cell. / Koike, Hiroki; Ohsawa, Takashi; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo.

In: Japanese Journal of Applied Physics, Vol. 53, No. 4 SPEC. ISSUE, 04ED13, 2014.

Research output: Contribution to journalArticle

Koike, Hiroki ; Ohsawa, Takashi ; Miura, Sadahiko ; Honjo, Hiroaki ; Ikeda, Shoji ; Hanyu, Takahiro ; Ohno, Hideo ; Endoh, Tetsuo. / Wide operational margin capability of 1 kbit spin-transfer-torque memory array chip with 1-PMOS and 1-bottom-pin-magnetic-tunnel-junction type cell. In: Japanese Journal of Applied Physics. 2014 ; Vol. 53, No. 4 SPEC. ISSUE.
@article{8442dc58a0cd4f46b2ee201eacc38194,
title = "Wide operational margin capability of 1 kbit spin-transfer-torque memory array chip with 1-PMOS and 1-bottom-pin-magnetic-tunnel-junction type cell",
abstract = "This paper discusses the optimal combination of 1 transistor (T) and 1 magnetic tunnel junction (MTJ) type cell for spin transfer torque memory. Taking into consideration of current magnitude for both the Tand the MTJ, either PMOS-bottom pin structure or NMOS-top pin structure can be a promising choice. Focusing on the PMOS-bottom pin structure from the viewpoint of avoiding process difficulty, we clarified the condition that the structure would be effective. In order to verify the structure's effectiveness, a stand-alone MTJ test element group and a 1 kbit memory array chip were designed and fabricated with 90nm CMOS/100nm MTJ process. With the pass bit percentage measurement of the memory chip, we successfully demonstrated that 1-PMOS and 1-bottom-pin-MTJ has the wide operation margin of 100{\%} pass at near 1.6V. It will be an effective solution for 1T-1MTJ memories.",
author = "Hiroki Koike and Takashi Ohsawa and Sadahiko Miura and Hiroaki Honjo and Shoji Ikeda and Takahiro Hanyu and Hideo Ohno and Tetsuo Endoh",
year = "2014",
doi = "10.7567/JJAP.53.04ED13",
language = "English",
volume = "53",
journal = "Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes",
issn = "0021-4922",
publisher = "Japan Society of Applied Physics",
number = "4 SPEC. ISSUE",

}

TY - JOUR

T1 - Wide operational margin capability of 1 kbit spin-transfer-torque memory array chip with 1-PMOS and 1-bottom-pin-magnetic-tunnel-junction type cell

AU - Koike, Hiroki

AU - Ohsawa, Takashi

AU - Miura, Sadahiko

AU - Honjo, Hiroaki

AU - Ikeda, Shoji

AU - Hanyu, Takahiro

AU - Ohno, Hideo

AU - Endoh, Tetsuo

PY - 2014

Y1 - 2014

N2 - This paper discusses the optimal combination of 1 transistor (T) and 1 magnetic tunnel junction (MTJ) type cell for spin transfer torque memory. Taking into consideration of current magnitude for both the Tand the MTJ, either PMOS-bottom pin structure or NMOS-top pin structure can be a promising choice. Focusing on the PMOS-bottom pin structure from the viewpoint of avoiding process difficulty, we clarified the condition that the structure would be effective. In order to verify the structure's effectiveness, a stand-alone MTJ test element group and a 1 kbit memory array chip were designed and fabricated with 90nm CMOS/100nm MTJ process. With the pass bit percentage measurement of the memory chip, we successfully demonstrated that 1-PMOS and 1-bottom-pin-MTJ has the wide operation margin of 100% pass at near 1.6V. It will be an effective solution for 1T-1MTJ memories.

AB - This paper discusses the optimal combination of 1 transistor (T) and 1 magnetic tunnel junction (MTJ) type cell for spin transfer torque memory. Taking into consideration of current magnitude for both the Tand the MTJ, either PMOS-bottom pin structure or NMOS-top pin structure can be a promising choice. Focusing on the PMOS-bottom pin structure from the viewpoint of avoiding process difficulty, we clarified the condition that the structure would be effective. In order to verify the structure's effectiveness, a stand-alone MTJ test element group and a 1 kbit memory array chip were designed and fabricated with 90nm CMOS/100nm MTJ process. With the pass bit percentage measurement of the memory chip, we successfully demonstrated that 1-PMOS and 1-bottom-pin-MTJ has the wide operation margin of 100% pass at near 1.6V. It will be an effective solution for 1T-1MTJ memories.

UR - http://www.scopus.com/inward/record.url?scp=84903277273&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84903277273&partnerID=8YFLogxK

U2 - 10.7567/JJAP.53.04ED13

DO - 10.7567/JJAP.53.04ED13

M3 - Article

AN - SCOPUS:84903277273

VL - 53

JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

SN - 0021-4922

IS - 4 SPEC. ISSUE

M1 - 04ED13

ER -