Wirelength driven I/O buffer placement for flip-chip with timing-constrained

Nan Liu, Shiyu Liu, Takeshi Yoshimura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Flip-chip package provides the highest chip density because I/O buffers in it could be placed anywhere inside a chip. The assignment of bump pads, I/O buffers and I/O pins will affect the satisfaction of timing requirement inside die core. In this paper, we proposed an effective three-step hierarchical approach to satisfy the timing-constrained I/O buffer placement in an area-I/O flip-chip design, meanwhile, wirelength could be optimized. First of all, I/O buffers are inserted to the floorplan plane greedily, and then, the wirelength between I/O buffers and I/O pins are optimized by a fixed-outline floorplanning algorithm. Secondly, a network flow model is conducted, and a min-cost-max-flow algorithm is used to assign I/O pins, I/O buffers and bump pads. Finally, the timing constraints are translated to length constraints, the results that satisfy timing constraints are selected. The experimental results show that, under the given timing constraints, higher timing-constrained satisfaction ratio (TCSR) is obtained, and the reduction of total wirelength is 14% on average.

Original languageEnglish
Title of host publicationIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
Pages631-634
Number of pages4
DOIs
Publication statusPublished - 2012
Event2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012 - Kaohsiung
Duration: 2012 Dec 22012 Dec 5

Other

Other2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
CityKaohsiung
Period12/12/212/12/5

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Liu, N., Liu, S., & Yoshimura, T. (2012). Wirelength driven I/O buffer placement for flip-chip with timing-constrained. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS (pp. 631-634). [6419114] https://doi.org/10.1109/APCCAS.2012.6419114

Wirelength driven I/O buffer placement for flip-chip with timing-constrained. / Liu, Nan; Liu, Shiyu; Yoshimura, Takeshi.

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2012. p. 631-634 6419114.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Liu, N, Liu, S & Yoshimura, T 2012, Wirelength driven I/O buffer placement for flip-chip with timing-constrained. in IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS., 6419114, pp. 631-634, 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012, Kaohsiung, 12/12/2. https://doi.org/10.1109/APCCAS.2012.6419114
Liu N, Liu S, Yoshimura T. Wirelength driven I/O buffer placement for flip-chip with timing-constrained. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2012. p. 631-634. 6419114 https://doi.org/10.1109/APCCAS.2012.6419114
Liu, Nan ; Liu, Shiyu ; Yoshimura, Takeshi. / Wirelength driven I/O buffer placement for flip-chip with timing-constrained. IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2012. pp. 631-634
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