Word error control algorithm through multi-reading for NAND flash memories

Chong Zhang, Tsutomu Yoshihara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents one error control scheme for NAND Flash memories with error correction code (ECC). With the increasing array bit error rates, multi bits ECCs like binary Bose-Chaudhuri-Hocquenghem (BCH) code, have been used widely to improve endurance and improve retention. However, with the correction ability and codeword length raise, the parity bits cost increase at the same time. With erasure concept, which means the read data is unstable for erasure cells, this paper proposes a codeword error decrease scheme for NAND Flash memories. This method with no more bits cost could provides more than 70% error decrease by altering reading data if errors exceed correction capability. It could be combined with BCH code or one-bits ECC like hamming code, for both 1-bit/cell or multi-bits/cell memories.

Original languageEnglish
Title of host publicationProceedings of International Conference on ASIC
Pages236-239
Number of pages4
DOIs
Publication statusPublished - 2011
Externally publishedYes
Event2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen
Duration: 2011 Oct 252011 Oct 28

Other

Other2011 IEEE 9th International Conference on ASIC, ASICON 2011
CityXiamen
Period11/10/2511/10/28

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Word error control algorithm through multi-reading for NAND flash memories'. Together they form a unique fingerprint.

Cite this