Word error control algorithm through multi-reading for NAND flash memories

Chong Zhang; Tsutomu Yoshihara

doi:10.1109/ASICON.2011.6157165

Word error control algorithm through multi-reading for NAND flash memories

Chong Zhang^*, Tsutomu Yoshihara

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper presents one error control scheme for NAND Flash memories with error correction code (ECC). With the increasing array bit error rates, multi bits ECCs like binary Bose-Chaudhuri-Hocquenghem (BCH) code, have been used widely to improve endurance and improve retention. However, with the correction ability and codeword length raise, the parity bits cost increase at the same time. With erasure concept, which means the read data is unstable for erasure cells, this paper proposes a codeword error decrease scheme for NAND Flash memories. This method with no more bits cost could provides more than 70% error decrease by altering reading data if errors exceed correction capability. It could be combined with BCH code or one-bits ECC like hamming code, for both 1-bit/cell or multi-bits/cell memories.

Original language	English
Title of host publication	Proceedings of International Conference on ASIC
Pages	236-239
Number of pages	4
DOIs	https://doi.org/10.1109/ASICON.2011.6157165
Publication status	Published - 2011
Externally published	Yes
Event	2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen Duration: 2011 Oct 25 → 2011 Oct 28

Other

Other	2011 IEEE 9th International Conference on ASIC, ASICON 2011
City	Xiamen
Period	11/10/25 → 11/10/28

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASICON.2011.6157165

Cite this

@inproceedings{22d68648d67e48998b55e81c00ee1213,

title = "Word error control algorithm through multi-reading for NAND flash memories",

abstract = "This paper presents one error control scheme for NAND Flash memories with error correction code (ECC). With the increasing array bit error rates, multi bits ECCs like binary Bose-Chaudhuri-Hocquenghem (BCH) code, have been used widely to improve endurance and improve retention. However, with the correction ability and codeword length raise, the parity bits cost increase at the same time. With erasure concept, which means the read data is unstable for erasure cells, this paper proposes a codeword error decrease scheme for NAND Flash memories. This method with no more bits cost could provides more than 70% error decrease by altering reading data if errors exceed correction capability. It could be combined with BCH code or one-bits ECC like hamming code, for both 1-bit/cell or multi-bits/cell memories.",

author = "Chong Zhang and Tsutomu Yoshihara",

year = "2011",

doi = "10.1109/ASICON.2011.6157165",

language = "English",

isbn = "9781612841908",

pages = "236--239",

booktitle = "Proceedings of International Conference on ASIC",

note = "2011 IEEE 9th International Conference on ASIC, ASICON 2011 ; Conference date: 25-10-2011 Through 28-10-2011",

}

TY - GEN

T1 - Word error control algorithm through multi-reading for NAND flash memories

AU - Zhang, Chong

AU - Yoshihara, Tsutomu

PY - 2011

Y1 - 2011

N2 - This paper presents one error control scheme for NAND Flash memories with error correction code (ECC). With the increasing array bit error rates, multi bits ECCs like binary Bose-Chaudhuri-Hocquenghem (BCH) code, have been used widely to improve endurance and improve retention. However, with the correction ability and codeword length raise, the parity bits cost increase at the same time. With erasure concept, which means the read data is unstable for erasure cells, this paper proposes a codeword error decrease scheme for NAND Flash memories. This method with no more bits cost could provides more than 70% error decrease by altering reading data if errors exceed correction capability. It could be combined with BCH code or one-bits ECC like hamming code, for both 1-bit/cell or multi-bits/cell memories.

AB - This paper presents one error control scheme for NAND Flash memories with error correction code (ECC). With the increasing array bit error rates, multi bits ECCs like binary Bose-Chaudhuri-Hocquenghem (BCH) code, have been used widely to improve endurance and improve retention. However, with the correction ability and codeword length raise, the parity bits cost increase at the same time. With erasure concept, which means the read data is unstable for erasure cells, this paper proposes a codeword error decrease scheme for NAND Flash memories. This method with no more bits cost could provides more than 70% error decrease by altering reading data if errors exceed correction capability. It could be combined with BCH code or one-bits ECC like hamming code, for both 1-bit/cell or multi-bits/cell memories.

UR - http://www.scopus.com/inward/record.url?scp=84860842559&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84860842559&partnerID=8YFLogxK

U2 - 10.1109/ASICON.2011.6157165

DO - 10.1109/ASICON.2011.6157165

M3 - Conference contribution

AN - SCOPUS:84860842559

SN - 9781612841908

SP - 236

EP - 239

BT - Proceedings of International Conference on ASIC

T2 - 2011 IEEE 9th International Conference on ASIC, ASICON 2011

Y2 - 25 October 2011 through 28 October 2011

ER -

Word error control algorithm through multi-reading for NAND flash memories

Abstract

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this