• 1243 引用
  • 18 h指数
1982 …2019
Pureに変更を加えた場合、すぐここに表示されます。

研究成果 1982 2019

  • 1243 引用
  • 18 h指数
  • 58 Conference contribution
  • 40 Article
2019

A CMOS 0.85-V 15.8-nW current and voltage reference without resistors

Wang, J. & Shinohara, H., 2019 4, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 8741737. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).

研究成果: Conference contribution

resistors
Resistors
CMOS
Electric potential
electric potential
2018

A 373 F 2 2D Power-Gated EE SRAM Physically Unclonable Function with Dark-Bit Detection Technique

Liu, K., Min, Y., Yang, X., Sun, H. & Shinohara, H., 2018 12 14, 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 161-164 4 p. 8579315. (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings).

研究成果: Conference contribution

Static random access storage
Bit error rate
Aging of materials
Temperature
1 引用 (Scopus)

High-throughput von Neumann post-processing for random number generator

Zhang, R., Chen, S., Wan, C. & Shinohara, H., 2018 6 5, 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc., p. 1-4 4 p.

研究成果: Conference contribution

Random number Generator
Post-processing
High Throughput
Throughput
Output
2017
Extractor
Oxides
Semiconductors
Metals
Voltage
3 引用 (Scopus)

Analysis and reduction of SRAM PUF Bit Error Rate

Shinohara, H., Zheng, B., Piao, Y., Liu, B. & Liu, S., 2017 6 5, 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017. Institute of Electrical and Electronics Engineers Inc., 7939688

研究成果: Conference contribution

Static random access storage
Bit error rate
Transistors
Hardware security
7 引用 (Scopus)

Correlation between static random access memory power-up state and transistor variation

Takeuchi, K., Mizutani, T., Saraya, T., Shinohara, H., Kobayashi, M. & Hiramoto, T., 2017 4 1, : : Japanese Journal of Applied Physics. 56, 4, 04CD03.

研究成果: Article

random access memory
power supplies
Transistors
transistors
Data storage equipment
3 引用 (Scopus)

Measurement of mismatch factor and noise of SRAM PUF using small bias voltage

Cui, Z., Zheng, B., Piao, Y., Liu, S., Xie, R. & Shinohara, H., 2017 6 20, 2017 International Conference of Microelectronic Test Structures, ICMTS 2017. Institute of Electrical and Electronics Engineers Inc., 7954264

研究成果: Conference contribution

Static random access storage
Bias voltage
Gaussian distribution
Electric potential
1 引用 (Scopus)

Measurement of static random access memory power-up state using an addressable cell array test structure

Takeuchi, K., Mizutani, T., Shinohara, H., Saraya, T., Kobayashi, M. & Hiramoto, T., 2017 8 1, : : IEEE Transactions on Semiconductor Manufacturing. 30, 3, p. 209-215 7 p., 7895199.

研究成果: Article

random access memory
Data storage equipment
cells
power supplies
Transistors
2 引用 (Scopus)

Parallel programmable nonvolatile memory using ordinary static random access memory cells

Mizutani, T., Takeuchi, K., Saraya, T., Shinohara, H., Kobayashi, M. & Hiramoto, T., 2017 4 1, : : Japanese Journal of Applied Physics. 56, 4, 04CD17.

研究成果: Article

random access memory
Data storage equipment
cells
power supplies
high voltages
2016
access time
random access memory
acceleration (physics)
Clocks
Data storage equipment
1 引用 (Scopus)
Resistors
Energy gap
Voltage
Networks (circuits)
Electric potential
2 引用 (Scopus)

AC direct multiple-string LED driver with low THD and minimum components

Yeh, Y., Chen, M., Li, X., Shinohara, H. & Yoshihara, T., 2016 2 8, ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE). Institute of Electrical and Electronics Engineers Inc., p. 117-118 2 p. 7401680

研究成果: Conference contribution

Harmonic distortion
Light emitting diodes
Operational amplifiers
Bias voltage
Diodes
1 引用 (Scopus)

An output capacitor-less low dropout regulator with quick-responding circuits

Zhang, C., Mei, J., Shinohara, H. & Yoshihara, T., 2016 2 8, ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE). Institute of Electrical and Electronics Engineers Inc., p. 51-52 2 p. 7401635

研究成果: Conference contribution

Capacitors
Networks (circuits)
Electric potential
Buffers
Switches
1 引用 (Scopus)

Design of a low-order sensorless controller by robust H∞ control for boost converters

Li, X., Chen, M., Shinohara, H. & Yoshihara, T., 2016 5 1, : : Journal of Power Electronics. 16, 3, p. 1025-1035 11 p.

研究成果: Article

Controllers
Riccati equations
Linear matrix inequalities
Knobs
Experiments

Design of a Luenberger observer based sensorless multi-loop control for boost converters

Li, X., Chen, M., Shinohara, H. & Tsutomu, Y., 2016 9 7, International Conference on Electronics, Information, and Communications, ICEIC 2016. Institute of Electrical and Electronics Engineers Inc., 7563030

研究成果: Conference contribution

Sampling
Networks (circuits)
Costs
Experiments
Sensorless control

Design of a sensorless controller synthesized by robust H∞ control for boost converters

Li, X., Chen, M., Shinohara, H. & Yoshihara, T., 2016 2 1, : : IEICE Transactions on Communications. E99B, 2, p. 356-363 8 p.

研究成果: Article

Controllers
Knobs
Riccati equations
Electric current control
Linear matrix inequalities
4 引用 (Scopus)

Measurement of SRAM power-up state for PUF applications using an addressable SRAM cell array test structure

Takeuchi, K., Mizutani, T., Saraya, T., Kobayashi, M., Hiramoto, T. & Shinohara, H., 2016 5 20, 2016 29th IEEE International Conference on Microelectronic Test Structures, ICMTS 2016 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 巻 2016-May. p. 130-134 5 p. 7476191

研究成果: Conference contribution

Static random access storage
Data storage equipment
2014
19 引用 (Scopus)

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

Ishibashi, K., Sugii, N., Usami, K., Amano, H., Kobayashi, K., Pham, C. K., Makiyama, H., Yamamoto, Y., Shinohara, H., Iwamatsu, T., Yamaguchi, Y., Oda, H., Hasegawa, T., Okanishi, S., Yanagita, H., Kamohara, S., Kadoshima, M., Maekawa, K., Yamashita, T., Le, D. H. および5人, Yomogita, T., Kudo, M., Kitamori, K., Kondo, S. & Manzawa, Y., 2014, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII. IEEE Computer Society, 6842954

研究成果: Conference contribution

Program processors
Silicon
Oxides
Sleep
9 引用 (Scopus)

Comparison and distribution of minimum operation voltage in fully depleted silicon-on-thin-buried-oxide and bulk static random access memory cells

Mizutani, T., Yamamoto, Y., Makiyama, H., Shinohara, H., Iwamatsu, T., Oda, H., Sugii, N. & Hiramoto, T., 2014, : : Japanese Journal of Applied Physics. 53, 4 SPEC. ISSUE, 04EC18.

研究成果: Article

random access memory
Data storage equipment
Silicon
Oxides
oxides
Digital circuits
Analog circuits
Electric potential
Energy efficiency
Networks (circuits)
4 引用 (Scopus)

Speed enhancement at Vdd = 0.4V and random Τpd variability reduction and analyisis of Τpd variability of silicon on thin buried oxide circuits

Makiyama, H., Yamamoto, Y., Shinohara, H., Iwamatsu, T., Oda, H., Sugii, N., Ishibashi, K. & Yamaguchi, Y., 2014, : : Japanese Journal of Applied Physics. 53, 4 SPEC. ISSUE, 04EC07.

研究成果: Article

Silicon
Oxides
oxides
propagation
Networks (circuits)
2013
3 引用 (Scopus)

0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS

Nomura, M., Muramatsu, A., Takeno, H., Hattori, S., Ogawa, D., Nasu, M., Hirairi, K., Kumashiro, S., Moriwaki, S., Yamamoto, Y., Miyano, S., Hiraku, Y., Hayashi, I., Yoshioka, K., Shikata, A., Ishikuro, H., Ahn, M., Okuma, Y., Zhang, X., Ryu, Y. および5人, Ishida, K., Takamiya, M., Kuroda, T., Shinohara, H. & Sakurai, T., 2013, Digest of Technical Papers - Symposium on VLSI Technology. 6576619

研究成果: Conference contribution

Program processors
Clocks
Electric potential
Logic design
Energy efficiency
5 引用 (Scopus)

0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS

Nomura, M., Muramatsu, A., Takeno, H., Hattori, S., Ogawa, D., Nasu, M., Hirairi, K., Kumashiro, S., Moriwaki, S., Yamamoto, Y., Miyano, S., Hiraku, Y., Hayashi, I., Yoshioka, K., Shikata, A., Ishikuro, H., Ahn, M., Okuma, Y., Zhang, X., Ryu, Y. および5人, Ishida, K., Takamiya, M., Kuroda, T., Shinohara, H. & Sakurai, T., 2013, IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 6578745

研究成果: Conference contribution

Program processors
Clocks
Electric potential
Logic design
Energy efficiency
2 引用 (Scopus)

A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure

Yoshimoto, S., Miyano, S., Takamiya, M., Shinohara, H., Kawaguchi, H. & Yoshimoto, M., 2013 11 7, Proceedings of the Custom Integrated Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 6658537

研究成果: Conference contribution

Static random access storage
Switches
Electric potential
9 引用 (Scopus)

Highly energy-efficient SRAM with hierarchical bit line charge-sharing method using non-selected bit line charges

Miyano, S., Moriwaki, S., Yamamoto, Y., Kawasumi, A., Suzuki, T., Sakurai, T. & Shinohara, H., 2013, : : IEEE Journal of Solid-State Circuits. 48, 4, p. 924-931 8 p., 6416957.

研究成果: Article

Static random access storage
Electric power utilization
Energy utilization
Electric potential
Threshold voltage
6 引用 (Scopus)

Increase of crosstalk noise due to imbalanced threshold voltage between nMOS and pMOS in subthreshold logic circuits

Fuketa, H., Takahashi, R., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2013, : : IEEE Journal of Solid-State Circuits. 48, 8, p. 1986-1994 9 p., 6515395.

研究成果: Article

Logic circuits
Crosstalk
Threshold voltage
Tuning
Electric potential
3 引用 (Scopus)

Minimizing energy of integer unit by higher voltage flip-flop: V DDmin-aware dual supply voltage technique

Fuketa, H., Hirairi, K., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2013, : : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21, 6, p. 1175-1179 5 p., 6236208.

研究成果: Article

Flip flop circuits
Electric potential
Combinatorial circuits
Logic gates
Networks (circuits)

Silicon on thin buried oxide (SOTB) technology for ultralow-power applications

Sugii, N., Iwamatsu, T., Yamamoto, Y., Makiyama, H., Shinohara, H., Aono, H., Oda, H., Kamohara, S., Yamaguchi, Y., Mizutani, T. & Hiramoto, T., 2013, ECS Transactions. 1 版 巻 54. p. 189-196 8 p.

研究成果: Conference contribution

Silicon
Oxides
Transistors
Electric potential
Electron devices
3 引用 (Scopus)

Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation

Makiyama, H., Yamamoto, Y., Shinohara, H., Iwamatsu, T., Oda, H., Sugii, N., Ishibashi, K., Mizutani, T., Hiramoto, T. & Yamaguchi, Y., 2013, Technical Digest - International Electron Devices Meeting, IEDM. 6724742

研究成果: Conference contribution

Silicon
Oxides
CMOS
retarding
oxides
41 引用 (Scopus)

Ultralow-voltage operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM down to 0.37 v utilizing adaptive back bias

Yamamoto, Y., Makiyama, H., Shinohara, H., Iwamatsu, T., Oda, H., Kamohara, S., Sugii, N., Yamaguchi, Y., Mizutani, T. & Hiramoto, T., 2013, Digest of Technical Papers - Symposium on VLSI Technology. 6576627

研究成果: Conference contribution

Static random access storage
Silicon
Electric potential
Oxides
Temperature
13 引用 (Scopus)

Ultralow-voltage operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM down to 0.37 v utilizing adaptive back bias

Yamamoto, Y., Makiyama, H., Shinohara, H., Iwamatsu, T., Oda, H., Kamohara, S., Sugii, N., Yamaguchi, Y., Mizutani, T. & Hiramoto, T., 2013, IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 6578753

研究成果: Conference contribution

Static random access storage
Silicon
Electric potential
Oxides
Temperature
1 引用 (Scopus)

Variation-aware subthreshold logic circuit design

Fuketa, H., Takahashi, R., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2013, Proceedings of International Conference on ASIC. IEEE Computer Society, 6811842

研究成果: Conference contribution

Logic design
Logic circuits
Degradation
Networks (circuits)
Electric potential

Vmin=0.4 v LSIs are the real with silicon-on-thin-buried-oxide (SOTB)-How is the application with 'Perpetuum-Mobile' micro-controller with SOTB?

Sugii, N., Iwamatsu, T., Yamamoto, Y., Makiyama, H., Shinohara, H., Oda, H., Kamohara, S., Yamaguchi, Y., Ishibashi, K., Mizutani, T. & Hiramoto, T., 2013, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013. IEEE Computer Society, 6716576

研究成果: Conference contribution

Silicon
Controllers
Oxides
Networks (circuits)
Static random access storage
2012
32 引用 (Scopus)

13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with Parity-based Error Prediction and Detection (PEPD) and fully integrated digital LDO

Hirairi, K., Okuma, Y., Fuketa, H., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2012, Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 巻 55. p. 486-487 2 p. 6177102

研究成果: Conference contribution

Voltage control
Electric potential
Delay circuits
Logic circuits
Energy efficiency
9 引用 (Scopus)

24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V DDmin limited ultra low voltage logic circuits

Yasufuku, T., Hirairi, K., Pu, Y., Zheng, Y. F., Takahashi, R., Sasaki, M., Fuketa, H., Muramatsu, A., Nomura, M., Shinohara, H., Takamiya, M. & Sakurai, T., 2012, Proceedings - International Symposium on Quality Electronic Design, ISQED. p. 586-591 6 p. 6187553

研究成果: Conference contribution

Logic circuits
Voltage control
Fabrication
Electric potential
Built-in self test
2 引用 (Scopus)

60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations

Yamamoto, Y., Kawasumi, A., Moriwaki, S., Suzuki, T., Miyano, S. & Shinohara, H., 2012, European Solid-State Circuits Conference. p. 317-320 4 p. 6341318

研究成果: Conference contribution

Static random access storage
Limiters
Data storage equipment
Energy dissipation
9 引用 (Scopus)

A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges

Moriwaki, S., Yamamoto, Y., Kawasumi, A., Suzuki, T., Miyano, S., Sakurai, T. & Shinohara, H., 2012, IEEE Symposium on VLSI Circuits, Digest of Technical Papers. p. 60-61 2 p. 6243789

研究成果: Conference contribution

Static random access storage
Networks (circuits)
Electric power utilization
Electric potential
1 引用 (Scopus)

Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits

Fuketa, H., Takahashi, R., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2012, Proceedings of the Custom Integrated Circuits Conference. 6330689

研究成果: Conference contribution

Threshold logic
Logic circuits
Crosstalk
Threshold voltage
SPICE
5 引用 (Scopus)

Large within-die gate delay variations in sub-threshold logic circuits at low temperature

Takahashi, R., Takata, H., Yasufuku, T., Fuketa, H., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2012, : : IEEE Transactions on Circuits and Systems II: Express Briefs. 59, 12, p. 918-921 4 p., 6392909.

研究成果: Article

Threshold logic
Logic circuits
Temperature
2011
10 引用 (Scopus)

12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2V to 310mV enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics

Fuketa, H., Hirairi, K., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2011, Proceedings of the International Symposium on Low Power Electronics and Design. p. 163-168 6 p. 5993630

研究成果: Conference contribution

Flip flop circuits
Energy efficiency
Electric potential
Voltage scaling
Processing
3 引用 (Scopus)

12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains

Muramatsu, A., Yasufuku, T., Nomura, M., Takamiya, M., Shinohara, H. & Sakurai, T., 2011, European Solid-State Circuits Conference. p. 191-194 4 p. 6044897

研究成果: Conference contribution

Logic circuits
Voltage control
Clocks
Electric potential
Flip flop circuits
21 引用 (Scopus)

A closed-form expression for estimating minimum operating voltage (V DDmin) of CMOS logic gates

Fuketa, H., Iida, S., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2011, Proceedings - Design Automation Conference. p. 984-989 6 p. 5981890

研究成果: Conference contribution

Logic gates
Closed-form
Voltage
Logic
Combinatorial circuits
9 引用 (Scopus)

Device-circuit interactions in extremely low voltage CMOS designs (invited)

Fuketa, H., Yasufuku, T., Iida, S., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2011, Technical Digest - International Electron Devices Meeting, IEDM. 6131609

研究成果: Conference contribution

low voltage
CMOS
logic design
Logic design
Networks (circuits)

Post-silicon clock deskew employing hot-carrier injection trimming with on-chip skew monitoring and auto-stressing scheme for sub/near threshold digital circuits

Pu, Y., Zhang, X., Ikeuchi, K., Muramatsu, A., Kawasumi, A., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2011 5, : : IEEE Transactions on Circuits and Systems II: Express Briefs. 58, 5, p. 294-298 5 p., 5772921.

研究成果: Article

Hot carriers
Trimming
Digital circuits
Clocks
Silicon
2010
11 引用 (Scopus)

0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme

Suzuki, T., Moriwaki, S., Kawasumi, A., Miyano, S. & Shinohara, H., 2010, ESSCIRC 2010 - 36th European Solid State Circuits Conference. p. 354-357 4 p. 5619716

研究成果: Conference contribution

Static random access storage
Transistors
Electric potential
Leakage currents
Data storage equipment
5 引用 (Scopus)
Flip flop circuits
Error detection
Energy utilization
Networks (circuits)
Voltage scaling
2009
55 引用 (Scopus)

A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist

Yabuuchi, M., Nii, K., Tsukamoto, Y., Ohbayashi, S., Nakase, Y. & Shinohara, H., 2009, IEEE Symposium on VLSI Circuits, Digest of Technical Papers. p. 158-159 2 p. 5205389

研究成果: Conference contribution

Static random access storage
Macros
Electric potential

Analysis technique for systematic variation over whole shot and wafer at 45 nm process node

Nakanishi, J., Notani, H., Nakase, Y. & Shinohara, H., 2009, ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC. p. 585-588 4 p. 5351353

研究成果: Conference contribution

39 引用 (Scopus)

Synchronous ultra-high-density 2RW dual-port 8T-SRAM with circumvention of simultaneous common-row-access

Nii, K., Tsukamoto, Y., Yabuuchi, M., Masuda, Y., Imaoka, S., Usui, K., Ohbayashi, S., Makino, H. & Shinohara, H., 2009 3, : : IEEE Journal of Solid-State Circuits. 44, 3, p. 977-986 10 p., 4787570.

研究成果: Article

Static random access storage
Macros
Random access storage
Transistors
Networks (circuits)
2008
26 引用 (Scopus)

A 45 nm 2-port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues

Ishikura, S., Kurumada, M., Terano, T., Yamagami, Y., Kotani, N., Satomi, K., Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Oashi, T., Makino, H., Shinohara, H. & Akamatsu, H., 2008 1, : : IEEE Journal of Solid-State Circuits. 43, 4, p. 938-943 6 p.

研究成果: Article

Static random access storage
Macros
Data storage equipment
Threshold voltage
Transistors