• 1284 引用
  • 18 h指数
1982 …2020

年単位の研究成果

Pureに変更を加えた場合、すぐここに表示されます。

研究成果

  • 1284 引用
  • 18 h指数
  • 52 Conference contribution
  • 41 Article
  • 6 Conference article
  • 1 Paper
フィルター
Conference contribution
2020

A 0.5-V 2.07-fJ/b 497-F2 EE/CMOS Hybrid SRAM Physically Unclonable Function with < 1E-7 Bit Error Rate Achieved through Hot Carrier Injection Burn-in

Liu, K., Pu, H. & Shinohara, H., 2020 3, 2020 IEEE Custom Integrated Circuits Conference, CICC 2020. Institute of Electrical and Electronics Engineers Inc., 9075875. (Proceedings of the Custom Integrated Circuits Conference; 巻数 2020-March).

研究成果: Conference contribution

2019

A CMOS 0.85-V 15.8-nW current and voltage reference without resistors

Wang, J. & Shinohara, H., 2019 4, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 8741737. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).

研究成果: Conference contribution

2018

A 373 F 2 2D Power-Gated EE SRAM Physically Unclonable Function with Dark-Bit Detection Technique

Liu, K., Min, Y., Yang, X., Sun, H. & Shinohara, H., 2018 12 14, 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 161-164 4 p. 8579315. (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings).

研究成果: Conference contribution

2 引用 (Scopus)

High-throughput von Neumann post-processing for random number generator

Zhang, R., Chen, S., Wan, C. & Shinohara, H., 2018 6 5, 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018. Institute of Electrical and Electronics Engineers Inc., p. 1-4 4 p.

研究成果: Conference contribution

3 引用 (Scopus)
2017

Analysis and reduction of SRAM PUF Bit Error Rate

Shinohara, H., Zheng, B., Piao, Y., Liu, B. & Liu, S., 2017 6 5, 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017. Institute of Electrical and Electronics Engineers Inc., 7939688

研究成果: Conference contribution

4 引用 (Scopus)

Measurement of mismatch factor and noise of SRAM PUF using small bias voltage

Cui, Z., Zheng, B., Piao, Y., Liu, S., Xie, R. & Shinohara, H., 2017 6 20, 2017 International Conference of Microelectronic Test Structures, ICMTS 2017. Institute of Electrical and Electronics Engineers Inc., 7954264

研究成果: Conference contribution

4 引用 (Scopus)
2016

AC direct multiple-string LED driver with low THD and minimum components

Yeh, Y., Chen, M., Li, X., Shinohara, H. & Yoshihara, T., 2016 2 8, ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE). Institute of Electrical and Electronics Engineers Inc., p. 117-118 2 p. 7401680

研究成果: Conference contribution

3 引用 (Scopus)

An output capacitor-less low dropout regulator with quick-responding circuits

Zhang, C., Mei, J., Shinohara, H. & Yoshihara, T., 2016 2 8, ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE). Institute of Electrical and Electronics Engineers Inc., p. 51-52 2 p. 7401635

研究成果: Conference contribution

2 引用 (Scopus)

Design of a Luenberger observer based sensorless multi-loop control for boost converters

Li, X., Chen, M., Shinohara, H. & Tsutomu, Y., 2016 9 7, International Conference on Electronics, Information, and Communications, ICEIC 2016. Institute of Electrical and Electronics Engineers Inc., 7563030

研究成果: Conference contribution

Measurement of SRAM power-up state for PUF applications using an addressable SRAM cell array test structure

Takeuchi, K., Mizutani, T., Saraya, T., Kobayashi, M., Hiramoto, T. & Shinohara, H., 2016 5 20, 2016 29th IEEE International Conference on Microelectronic Test Structures, ICMTS 2016 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 巻 2016-May. p. 130-134 5 p. 7476191

研究成果: Conference contribution

6 引用 (Scopus)
2014

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

Ishibashi, K., Sugii, N., Usami, K., Amano, H., Kobayashi, K., Pham, C. K., Makiyama, H., Yamamoto, Y., Shinohara, H., Iwamatsu, T., Yamaguchi, Y., Oda, H., Hasegawa, T., Okanishi, S., Yanagita, H., Kamohara, S., Kadoshima, M., Maekawa, K., Yamashita, T., Le, D. H. および5人, Yomogita, T., Kudo, M., Kitamori, K., Kondo, S. & Manzawa, Y., 2014 1 1, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII. IEEE Computer Society, 6842954. (IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII).

研究成果: Conference contribution

20 引用 (Scopus)
2013

0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS

Nomura, M., Muramatsu, A., Takeno, H., Hattori, S., Ogawa, D., Nasu, M., Hirairi, K., Kumashiro, S., Moriwaki, S., Yamamoto, Y., Miyano, S., Hiraku, Y., Hayashi, I., Yoshioka, K., Shikata, A., Ishikuro, H., Ahn, M., Okuma, Y., Zhang, X., Ryu, Y. および5人, Ishida, K., Takamiya, M., Kuroda, T., Shinohara, H. & Sakurai, T., 2013 9 17, 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers. p. C36-C37 6578745. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

研究成果: Conference contribution

5 引用 (Scopus)

0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS

Nomura, M., Muramatsu, A., Takeno, H., Hattori, S., Ogawa, D., Nasu, M., Hirairi, K., Kumashiro, S., Moriwaki, S., Yamamoto, Y., Miyano, S., Hiraku, Y., Hayashi, I., Yoshioka, K., Shikata, A., Ishikuro, H., Ahn, M., Okuma, Y., Zhang, X., Ryu, Y. および5人, Ishida, K., Takamiya, M., Kuroda, T., Shinohara, H. & Sakurai, T., 2013 9 9, 2013 Symposium on VLSI Technology, VLSIT 2013 - Digest of Technical Papers. p. C36-C37 6576619. (Digest of Technical Papers - Symposium on VLSI Technology).

研究成果: Conference contribution

3 引用 (Scopus)

A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure

Yoshimoto, S., Miyano, S., Takamiya, M., Shinohara, H., Kawaguchi, H. & Yoshimoto, M., 2013 11 7, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013. Institute of Electrical and Electronics Engineers Inc., 6658537. (Proceedings of the Custom Integrated Circuits Conference).

研究成果: Conference contribution

2 引用 (Scopus)

Silicon on thin buried oxide (SOTB) technology for ultralow-power applications

Sugii, N., Iwamatsu, T., Yamamoto, Y., Makiyama, H., Shinohara, H., Aono, H., Oda, H., Kamohara, S., Yamaguchi, Y., Mizutani, T. & Hiramoto, T., 2013 10 21, 2013 International Conference on Semiconductor Technology for Ultra Large Scale Integrated Circuits and Thin Film Transistors, ULSIC vs. TFT 4. 1 版 p. 189-196 8 p. (ECS Transactions; 巻数 54, 番号 1).

研究成果: Conference contribution

Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation

Makiyama, H., Yamamoto, Y., Shinohara, H., Iwamatsu, T., Oda, H., Sugii, N., Ishibashi, K., Mizutani, T., Hiramoto, T. & Yamaguchi, Y., 2013 12 1, 2013 IEEE International Electron Devices Meeting, IEDM 2013. p. 33.2.1-33.2.4 6724742. (Technical Digest - International Electron Devices Meeting, IEDM).

研究成果: Conference contribution

3 引用 (Scopus)

Ultralow-voltage operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM down to 0.37 v utilizing adaptive back bias

Yamamoto, Y., Makiyama, H., Shinohara, H., Iwamatsu, T., Oda, H., Kamohara, S., Sugii, N., Yamaguchi, Y., Mizutani, T. & Hiramoto, T., 2013 9 17, 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers. p. T212-T213 6578753. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

研究成果: Conference contribution

14 引用 (Scopus)

Ultralow-voltage operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM down to 0.37 v utilizing adaptive back bias

Yamamoto, Y., Makiyama, H., Shinohara, H., Iwamatsu, T., Oda, H., Kamohara, S., Sugii, N., Yamaguchi, Y., Mizutani, T. & Hiramoto, T., 2013 9 9, 2013 Symposium on VLSI Technology, VLSIT 2013 - Digest of Technical Papers. p. T212-T213 6576627. (Digest of Technical Papers - Symposium on VLSI Technology).

研究成果: Conference contribution

47 引用 (Scopus)

Variation-aware subthreshold logic circuit design

Fuketa, H., Takahashi, R., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2013 1 1, 2013 IEEE 10th International Conference on ASIC, ASICON 2013. IEEE Computer Society, 6811842. (Proceedings of International Conference on ASIC).

研究成果: Conference contribution

1 引用 (Scopus)

Vmin=0.4 v LSIs are the real with silicon-on-thin-buried-oxide (SOTB)-How is the application with 'Perpetuum-Mobile' micro-controller with SOTB?

Sugii, N., Iwamatsu, T., Yamamoto, Y., Makiyama, H., Shinohara, H., Oda, H., Kamohara, S., Yamaguchi, Y., Ishibashi, K., Mizutani, T. & Hiramoto, T., 2013 1 1, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013. IEEE Computer Society, 6716576. (2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013).

研究成果: Conference contribution

2012

13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with Parity-based Error Prediction and Detection (PEPD) and fully integrated digital LDO

Hirairi, K., Okuma, Y., Fuketa, H., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2012 5 11, 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers. p. 486-487 2 p. 6177102. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; 巻数 55).

研究成果: Conference contribution

32 引用 (Scopus)

24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V DDmin limited ultra low voltage logic circuits

Yasufuku, T., Hirairi, K., Pu, Y., Zheng, Y. F., Takahashi, R., Sasaki, M., Fuketa, H., Muramatsu, A., Nomura, M., Shinohara, H., Takamiya, M. & Sakurai, T., 2012 7 16, Proceedings of the 13th International Symposium on Quality Electronic Design, ISQED 2012. p. 586-591 6 p. 6187553. (Proceedings - International Symposium on Quality Electronic Design, ISQED).

研究成果: Conference contribution

9 引用 (Scopus)

60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations

Yamamoto, Y., Kawasumi, A., Moriwaki, S., Suzuki, T., Miyano, S. & Shinohara, H., 2012 12 14, 2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012. p. 317-320 4 p. 6341318. (European Solid-State Circuits Conference).

研究成果: Conference contribution

2 引用 (Scopus)

A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges

Moriwaki, S., Yamamoto, Y., Kawasumi, A., Suzuki, T., Miyano, S., Sakurai, T. & Shinohara, H., 2012 9 28, 2012 Symposium on VLSI Circuits, VLSIC 2012. p. 60-61 2 p. 6243789. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

研究成果: Conference contribution

9 引用 (Scopus)

Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits

Fuketa, H., Takahashi, R., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2012 11 26, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012. 6330689. (Proceedings of the Custom Integrated Circuits Conference).

研究成果: Conference contribution

1 引用 (Scopus)
2011

12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2V to 310mV enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics

Fuketa, H., Hirairi, K., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2011 9 19, IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011. p. 163-168 6 p. 5993630. (Proceedings of the International Symposium on Low Power Electronics and Design).

研究成果: Conference contribution

10 引用 (Scopus)

12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains

Muramatsu, A., Yasufuku, T., Nomura, M., Takamiya, M., Shinohara, H. & Sakurai, T., 2011 12 12, ESSCIRC 2011 - Proceedings of the 37th European Solid-State Circuits Conference. p. 191-194 4 p. 6044897. (European Solid-State Circuits Conference).

研究成果: Conference contribution

3 引用 (Scopus)

A closed-form expression for estimating minimum operating voltage (V DDmin) of CMOS logic gates

Fuketa, H., Iida, S., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2011 1 1, 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011. Institute of Electrical and Electronics Engineers Inc., p. 984-989 6 p. 5981890. (Proceedings - Design Automation Conference).

研究成果: Conference contribution

21 引用 (Scopus)

Device-circuit interactions in extremely low voltage CMOS designs (invited)

Fuketa, H., Yasufuku, T., Iida, S., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2011 12 1, 2011 International Electron Devices Meeting, IEDM 2011. p. 25.1.1-25.1.4 6131609. (Technical Digest - International Electron Devices Meeting, IEDM).

研究成果: Conference contribution

9 引用 (Scopus)
2010

0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme

Suzuki, T., Moriwaki, S., Kawasumi, A., Miyano, S. & Shinohara, H., 2010 12 27, ESSCIRC 2010 - 36th European Solid State Circuits Conference. p. 354-357 4 p. 5619716. (ESSCIRC 2010 - 36th European Solid State Circuits Conference).

研究成果: Conference contribution

11 引用 (Scopus)
2009

A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist

Yabuuchi, M., Nii, K., Tsukamoto, Y., Ohbayashi, S., Nakase, Y. & Shinohara, H., 2009 11 18, 2009 Symposium on VLSI Circuits. p. 158-159 2 p. 5205389. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

研究成果: Conference contribution

60 引用 (Scopus)

Analysis technique for systematic variation over whole shot and wafer at 45 nm process node

Nakanishi, J., Notani, H., Nakase, Y. & Shinohara, H., 2009 12 1, ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC. p. 585-588 4 p. 5351353. (ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC).

研究成果: Conference contribution

2008

A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Oda, Y., Usui, K., Kawamura, T., Tsuboi, N., Iwasaki, T., Hashimoto, K., Makino, H. & Shinohara, H., 2008 9 23, 2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC. p. 202-203 2 p. 4586011. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

研究成果: Conference contribution

78 引用 (Scopus)

On-chip digital Idn and Idp measurement by 65 nm CMOS speed monitor circuit

Notani, H., Fujii, M., Suzuki, H., Makino, H. & Shinohara, H., 2008 12 1, Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008. p. 405-408 4 p. 4708813. (Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008).

研究成果: Conference contribution

10 引用 (Scopus)

On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect

Fujii, M., Suzuki, H., Notani, H., Makino, H. & Shinohara, H., 2008 12 31, ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference. p. 258-261 4 p. 4681841. (ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference).

研究成果: Conference contribution

3 引用 (Scopus)

Phase-adjustable Error Detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for Dynamic Voltage Scaling

Kurimoto, M., Suzuki, H., Akiyama, R., Yamanaka, T., Ohkuma, H., Takata, H. & Shinohara, H., 2008 9 17, Proceedings of the 45th Design Automation Conference, DAC. p. 884-889 6 p. 4555944. (Proceedings - Design Automation Conference).

研究成果: Conference contribution

8 引用 (Scopus)

Post-Silicon Programmed Body-Biasing Platform suppressing device variability in 45 nm CMOS technology

Suzuki, H., Kurimoto, M., Yamanaka, T., Takata, H., Makino, H. & Shinohara, H., 2008 12 17, ISLPED'08: Proceedings of the 2008 International Symposium on Low Power Electronics and Design. p. 15-20 6 p. (Proceedings of the International Symposium on Low Power Electronics and Design).

研究成果: Conference contribution

2007

A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous RAV access issues

Ishikura, S., Kurumada, M., Terano, T., Yamagami, Y., Kotani, N., Satomi, K., Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Oashi, T., Makino, H., Shinohara, H. & Akamatsu, H., 2007 12 1, 2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers. p. 254-255 2 p. 4342740. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

研究成果: Conference contribution

12 引用 (Scopus)

A 45nm low-standby-power embedded SRAM with improved immunity against process and temperature variations

Yabuuchi, M., Nii, K., Tsukamoto, Y., Ohbayashi, S., Imaoka, S., Makino, H., Yamagami, Y., Ishikura, S., Terano, T., Oashi, T., Hashimoto, K., Sebe, A., Okazaki, G., Satomi, K., Akamatsu, H. & Shinohara, H., 2007 9 27, 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. p. 326-327+606+321 4242397. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

研究成果: Conference contribution

49 引用 (Scopus)

A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die

Ohbayashi, S., Yabuuchi, M., Kono, K., Oda, Y., Imaoka, S., Usui, K., Yonezu, T., Iwamoto, T., Nii, K., Tsukamoto, Y., Arakawa, M., Uchida, T., Qkada, M., Ishii, A., Makino, H., Ishibashi, K. & Shinohara, H., 2007 9 27, 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. p. 488-489+617+485 4242478. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

研究成果: Conference contribution

4 引用 (Scopus)

A large scale, flip-flop RAM imitating a logic LSI for fast development of process technology

Fujii, M., Nii, K., Makino, H., Ohbayashi, S., Igarashi, M., Kawamura, T., Yokota, M., Tsuda, N., Yoshizawa, T., Tsutsui, T., Takeshita, N., Murata, N., Tanaka, T., Fujiwara, T., Asahina, K., Okada, M., Tomita, K., Takeuchi, M. & Shinohara, H., 2007, 2007 IEEE International Conference on Microelectronic Test Structures, ICMTS - Conference Proceedings. p. 131-134 4 p. 4252419. (IEEE International Conference on Microelectronic Test Structures).

研究成果: Conference contribution

9 引用 (Scopus)
2006

1.047GHz, 1.2V, 90nm CMOS, 2-way VLIW DSP core using saturation anticipator circuit

Suzuki, H., Takata, H., Shinohara, H., Teraoka, E., Matsuo, M., Yoshida, T., Sato, H., Honda, N., Masui, N. & Shimizu, T., 2006 12 1, 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers. p. 152-153 2 p. 1705355. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

研究成果: Conference contribution

2 引用 (Scopus)

A 65 nm SoC embedded 6T-SRAM design for manufacturing with read and write cell stabilizing circuits

Ohbayashi, S., Yabuuchi, M., Nii, K., Tsukamoto, Y., Imaoka, S., Oda, Y., Igarashi, M., Takeuchi, M., Kawashima, H., Makino, H., Yamaguchi, Y., Tsukamoto, K., Inuishi, M., Ishibashi, K. & Shinohara, H., 2006 12 1, 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers. p. 17-18 2 p. 1705290. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

研究成果: Conference contribution

41 引用 (Scopus)

A 65 nm ultra-high-density dual-port SRAM with 0.71um2 8T-cell for SoC

Nii, K., Masuda, Y., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Imaoka, S., Igarashi, M., Tomita, K., Tsuboi, N., Makino, H., Ishibashi, K. & Shinohara, H., 2006 12 1, 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers. p. 130-131 2 p. 1705344. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

研究成果: Conference contribution

16 引用 (Scopus)
2005

A wide lock-in range PLL using self-calibrating technique for processors

Nakanishi, J., Notani, H., Makino, H. & Shinohara, H., 2005 1 1, 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005. IEEE Computer Society, p. 285-288 4 p. 4017587. (2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005).

研究成果: Conference contribution

Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability

Tsukamoto, Y., Nii, K., Imaoka, S., Oda, Y., Ohbayashi, S., Yoshizawa, T., Makino, H., Ishibashi, K. & Shinohara, H., 2005 12 1, Proceedings of theICCAD-2005: International Conference on Computer-Aided Design. p. 398-405 8 p. 1560101. (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD; 巻数 2005).

研究成果: Conference contribution

43 引用 (Scopus)
1994

1.2GFLOPS neural network chip exhibiting fast convergence

Kondo, Y., Koshiba, Y., Arima, Y., Murasaki, M., Yamada, T., Amishiro, H., Shinohara, H. & Mori, H., 1994 1 1, Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Anon (版). Publ by IEEE, p. 218-219 2 p. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

研究成果: Conference contribution

14 引用 (Scopus)
1993

20 Tera-CPS analog neural network board

Murasaki, M., Arima, Y. & Shinohara, H., 1993 12 1, Proceedings of the International Joint Conference on Neural Networks. Publ by IEEE, p. 3027-3030 4 p. (Proceedings of the International Joint Conference on Neural Networks; 巻数 3).

研究成果: Conference contribution

1 引用 (Scopus)

8.8-ns 54×54-bit multiplier using new redundant binary architecture

Makino, H., Nakase, Y. & Shinohara, H., 1993 12 1, Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Anon (版). Publ by IEEE, p. 202-205 4 p. (Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors).

研究成果: Conference contribution

23 引用 (Scopus)

Voltage compensated series-gate bipolar circuit operating at sub-2V

Sato, H., Ueda, K., Sasaki, N., Niwano, K. & Shinohara, H., 1993 12 1, Proceedings of the 1993 Bipolar/Bicoms Circuits and Technology. Anon (版). Publ by IEEE, p. 232-235 4 p. (Proceedings of the 1993 Bipolar/Bicoms Circuits and Technology).

研究成果: Conference contribution

1 引用 (Scopus)