年単位の研究成果
研究成果 1982 2019
2017
Accurate nanopower supply-insensitive CMOS unit Vth extractor and α Vth extractor with continuous variety
Wang, J., Ding, L., Li, Q., Shinohara, H. & Inoue, Y., 2017 5 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 5, p. 1145-1155 11 p.研究成果: Article
Extractor
Oxides
Semiconductors
Metals
Voltage
7
引用
(Scopus)
Correlation between static random access memory power-up state and transistor variation
Takeuchi, K., Mizutani, T., Saraya, T., Shinohara, H., Kobayashi, M. & Hiramoto, T., 2017 4 1, ： : Japanese Journal of Applied Physics. 56, 4, 04CD03.研究成果: Article
random access memory
power supplies
Transistors
transistors
Data storage equipment
1
引用
(Scopus)
Measurement of static random access memory power-up state using an addressable cell array test structure
Takeuchi, K., Mizutani, T., Shinohara, H., Saraya, T., Kobayashi, M. & Hiramoto, T., 2017 8 1, ： : IEEE Transactions on Semiconductor Manufacturing. 30, 3, p. 209-215 7 p., 7895199.研究成果: Article
random access memory
Data storage equipment
cells
power supplies
Transistors
2
引用
(Scopus)
Parallel programmable nonvolatile memory using ordinary static random access memory cells
Mizutani, T., Takeuchi, K., Saraya, T., Shinohara, H., Kobayashi, M. & Hiramoto, T., 2017 4 1, ： : Japanese Journal of Applied Physics. 56, 4, 04CD17.研究成果: Article
random access memory
Data storage equipment
cells
power supplies
high voltages
2016
39% access time improvement, 11% energy reduction, 32 kbit 1-read/1-write 2-port static random-access memory using two-stage read boost and write-boost after read sensing scheme
Yamamoto, Y., Moriwaki, S., Kawasumi, A., Miyano, S. & Shinohara, H., 2016 4 1, ： : Japanese Journal of Applied Physics. 55, 4, 04EF13.研究成果: Article
access time
random access memory
acceleration (physics)
Clocks
Data storage equipment
1
引用
(Scopus)
A 3.5 ppm/°C 0.85V bandgap reference circuit without resistors
Wang, J., Li, Q., Ding, L., Shinohara, H. & Inoue, Y., 2016 7 1, ： : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E99A, 7, p. 1430-1437 8 p.研究成果: Article
Resistors
Energy gap
Voltage
Networks (circuits)
Electric potential
1
引用
(Scopus)
Design of a low-order sensorless controller by robust H∞ control for boost converters
Li, X., Chen, M., Shinohara, H. & Yoshihara, T., 2016 5 1, ： : Journal of Power Electronics. 16, 3, p. 1025-1035 11 p.研究成果: Article
Controllers
Riccati equations
Linear matrix inequalities
Knobs
Experiments
Design of a sensorless controller synthesized by robust H∞ control for boost converters
Li, X., Chen, M., Shinohara, H. & Yoshihara, T., 2016 2 1, ： : IEICE Transactions on Communications. E99B, 2, p. 356-363 8 p.研究成果: Article
Controllers
Knobs
Riccati equations
Electric current control
Linear matrix inequalities
2014
9
引用
(Scopus)
Comparison and distribution of minimum operation voltage in fully depleted silicon-on-thin-buried-oxide and bulk static random access memory cells
Mizutani, T., Yamamoto, Y., Makiyama, H., Shinohara, H., Iwamatsu, T., Oda, H., Sugii, N. & Hiramoto, T., 2014, ： : Japanese Journal of Applied Physics. 53, 4 SPEC. ISSUE, 04EC18.研究成果: Article
random access memory
Data storage equipment
Silicon
Oxides
oxides
Extremely low power digital and analog circuits
Shinohara, H., 2014, ： : IEICE Transactions on Electronics. E97-C, 6, p. 469-475 7 p.研究成果: Article
Digital circuits
Analog circuits
Electric potential
Energy efficiency
Networks (circuits)
4
引用
(Scopus)
Speed enhancement at Vdd = 0.4V and random Τpd variability reduction and analyisis of Τpd variability of silicon on thin buried oxide circuits
Makiyama, H., Yamamoto, Y., Shinohara, H., Iwamatsu, T., Oda, H., Sugii, N., Ishibashi, K. & Yamaguchi, Y., 2014, ： : Japanese Journal of Applied Physics. 53, 4 SPEC. ISSUE, 04EC07.研究成果: Article
Silicon
Oxides
oxides
propagation
Networks (circuits)
2013
9
引用
(Scopus)
Highly energy-efficient SRAM with hierarchical bit line charge-sharing method using non-selected bit line charges
Miyano, S., Moriwaki, S., Yamamoto, Y., Kawasumi, A., Suzuki, T., Sakurai, T. & Shinohara, H., 2013, ： : IEEE Journal of Solid-State Circuits. 48, 4, p. 924-931 8 p., 6416957.研究成果: Article
Static random access storage
Electric power utilization
Energy utilization
Electric potential
Threshold voltage
6
引用
(Scopus)
Increase of crosstalk noise due to imbalanced threshold voltage between nMOS and pMOS in subthreshold logic circuits
Fuketa, H., Takahashi, R., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2013, ： : IEEE Journal of Solid-State Circuits. 48, 8, p. 1986-1994 9 p., 6515395.研究成果: Article
Logic circuits
Crosstalk
Threshold voltage
Tuning
Electric potential
3
引用
(Scopus)
Minimizing energy of integer unit by higher voltage flip-flop: V DDmin-aware dual supply voltage technique
Fuketa, H., Hirairi, K., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2013, ： : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21, 6, p. 1175-1179 5 p., 6236208.研究成果: Article
Flip flop circuits
Electric potential
Combinatorial circuits
Logic gates
Networks (circuits)
2012
5
引用
(Scopus)
Large within-die gate delay variations in sub-threshold logic circuits at low temperature
Takahashi, R., Takata, H., Yasufuku, T., Fuketa, H., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2012, ： : IEEE Transactions on Circuits and Systems II: Express Briefs. 59, 12, p. 918-921 4 p., 6392909.研究成果: Article
Threshold logic
Logic circuits
Temperature
2011
Post-silicon clock deskew employing hot-carrier injection trimming with on-chip skew monitoring and auto-stressing scheme for sub/near threshold digital circuits
Pu, Y., Zhang, X., Ikeuchi, K., Muramatsu, A., Kawasumi, A., Takamiya, M., Nomura, M., Shinohara, H. & Sakurai, T., 2011 5, ： : IEEE Transactions on Circuits and Systems II: Express Briefs. 58, 5, p. 294-298 5 p., 5772921.研究成果: Article
Hot carriers
Trimming
Digital circuits
Clocks
Silicon
2010
5
引用
(Scopus)
Phase-adjustable error detection flip-flops with 2-stage hold-driven optimization, slack-based grouping scheme and slack distribution control for dynamic voltage scaling
Kurimoto, M., Suzuki, H., Akiyama, R., Yamanaka, T., Ohkuma, H., Takata, H. & Shinohara, H., 2010 2 1, ： : ACM Transactions on Design Automation of Electronic Systems. 15, 2, 17.研究成果: Article
Flip flop circuits
Error detection
Energy utilization
Networks (circuits)
Voltage scaling
2009
39
引用
(Scopus)
Synchronous ultra-high-density 2RW dual-port 8T-SRAM with circumvention of simultaneous common-row-access
Nii, K., Tsukamoto, Y., Yabuuchi, M., Masuda, Y., Imaoka, S., Usui, K., Ohbayashi, S., Makino, H. & Shinohara, H., 2009 3, ： : IEEE Journal of Solid-State Circuits. 44, 3, p. 977-986 10 p., 4787570.研究成果: Article
Static random access storage
Macros
Random access storage
Transistors
Networks (circuits)
2008
26
引用
(Scopus)
A 45 nm 2-port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues
Ishikura, S., Kurumada, M., Terano, T., Yamagami, Y., Kotani, N., Satomi, K., Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Oashi, T., Makino, H., Shinohara, H. & Akamatsu, H., 2008 1, ： : IEEE Journal of Solid-State Circuits. 43, 4, p. 938-943 6 p.研究成果: Article
Static random access storage
Macros
Data storage equipment
Threshold voltage
Transistors
46
引用
(Scopus)
A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations
Nii, K., Yabuuchi, M., Tsukamoto, Y., Ohbayashi, S., Imaoka, S., Makino, H., Yamagami, Y., Ishikura, S., Terano, T., Oashi, T., Hashimoto, K., Sebe, A., Okazaki, G., Satomi, K., Akamatsu, H. & Shinohara, H., 2008, ： : IEEE Journal of Solid-State Circuits. 43, 1, p. 180-191 12 p.研究成果: Article
Static random access storage
Networks (circuits)
Electric potential
Data storage equipment
Temperature
9
引用
(Scopus)
A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die
Ohbayashi, S., Yabuuchi, M., Kono, K., Oda, Y., Imaoka, S., Usui, K., Yonezu, T., Iwamoto, T., Nii, K., Tsukamoto, Y., Arakawa, M., Uchida, T., Okada, M., Ishii, A., Yoshihara, T., Makino, H., Ishibashi, K. & Shinohara, H., 2008, ： : IEEE Journal of Solid-State Circuits. 43, 1, p. 96-108 13 p.研究成果: Article
Static random access storage
Electric fuses
Redundancy
Transistors
Trimming
1
引用
(Scopus)
A large-scale, flip-flop RAM imitating a logic LSI for fast development of process technology
Fujii, M., Nii, K., Makino, H., Ohbayashi, S., Igarashi, M., Kawamura, T., Yokota, M., Tsuda, N., Yoshizawa, T., Tsutsui, T., Takeshita, N., Murata, N., Tanaka, T., Fujiwara, T., Asahina, K., Okada, M., Tomita, K., Takeuchl, M., Yamamoto, S., Sugimoto, H. および1人, , 2008 8, ： : IEICE Transactions on Electronics. E91-C, 8, p. 1338-1347 10 p.研究成果: Article
Flip flop circuits
Random access storage
Static random access storage
Neutrons
Metals
1
引用
(Scopus)
Analytical model of static noise margin in CMOS SRAM for variation consideration
Shinohara, H., Nii, K. & Onodera, H., 2008 9, ： : IEICE Transactions on Electronics. E91-C, 9, p. 1488-1500 13 p.研究成果: Article
Static random access storage
Analytical models
Circuit simulation
Transistors
1
引用
(Scopus)
A robust silicon-on-insulator static-random-access-memory architecture by using advanced actively body-bias controlled technology
Hirano, Y., Tsujiuchi, M., Ishikawa, K., Shinohara, H., Terada, T., Maki, Y., Iwamatsu, T., Eikyu, K., Uchida, T., Obayashi, S., Nii, K., Tsukamoto, Y., Yabuuchi, M., Ipposhi, T., Oda, H. & Inoue, Y., 2008 4 18, ： : Japanese Journal of Applied Physics. 47, 4 PART 1, p. 2092-2096 5 p.研究成果: Article
Memory architecture
random access memory
insulators
margins
Silicon
2007
84
引用
(Scopus)
A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits
Ohbayashi, S., Yabuuchi, M., Nil, K., Tsukamoto, Y., Imaoka, S., Oda, Y., Yoshihara, T., Igarashi, M., Takeuchi, M., Kawashima, H., Yamaguchi, Y., Tsukamoto, K., Inuishi, M., Makino, H., Ishibashi, K. & Shinohara, H., 2007 4, ： : IEEE Journal of Solid-State Circuits. 42, 4, p. 820-829 10 p.研究成果: Article
Static random access storage
Networks (circuits)
System-on-chip
1996
10
引用
(Scopus)
A 64-bit carry look ahead adder using pass transistor BiCMOS gates
Ueda, K., Suzuki, H., Suda, K., Shinohara, H. & Mashiko, K., 1996 6, ： : IEEE Journal of Solid-State Circuits. 31, 6, p. 810-817 8 p.研究成果: Article
Adders
Transistors
Rails
Time delay
Electric potential
101
引用
(Scopus)
An 8.8-ns 54 × 54-bit multiplier with high speed redundant binary architecture
Makino, H., Nakase, Y., Suzuki, H., Morinaka, H., Shinohara, H. & Mashiko, K., 1996 6, ： : IEEE Journal of Solid-State Circuits. 31, 6, p. 773-782 10 p.研究成果: Article
Networks (circuits)
Adders
Energy dissipation
Transistors
Electric potential
1992
25
引用
(Scopus)
A refreshable analog VLSI neural network chip with 400 neurons and 40K synapses
Arima, Y., Murasaki, M., Yamada, T., Maeda, A. & Shinohara, H., 1992 12, ： : IEEE Journal of Solid-State Circuits. 27, 12, p. 1854-1861 8 p.研究成果: Article
Analog storage
LSI circuits
Neurons
Neural networks
Metals
1991
17
引用
(Scopus)
A flexible multiport RAM compiler for data path
Shinohara, H., Matsumoto, N., Fujimori, K., Tsujihashi, Y., Nakao, H., Kato, S., Horiba, Y. & Tada, A., 1991 3, ： : IEEE Journal of Solid-State Circuits. 26, 3, p. 343-349 7 p.研究成果: Article
Random access storage
Data storage equipment
Controllability
Aspect ratio
Electric power utilization
1990
12
引用
(Scopus)
A 24-b 50-ns digital image signal processor
Nakagawa, S. I., Terane, H., Matsumura, T., Segawa, H., Shinohara, H., Shinohara, H., Kato, S. I., Hatanaka, M., Ohira, H., Kato, Y., Iwatsuki, M., Tabuchi, K. & Horiba, Y., 1990 12, ： : IEEE Journal of Solid-State Circuits. 25, 6, p. 1484-1493 10 p.研究成果: Article
Parallel architectures
Networks (circuits)
Decoding
Clocks
Transistors
1987
12
引用
(Scopus)
34-NS 1-MBIT CMOS SRAM USING TRIPLE POLYSILICON.
Wada, T., Hirose, T., Shinohara, H., Kawai, Y., Yuzuriha, K., Kohno, Y. & Kayano, S., 1987 10, ： : IEEE Journal of Solid-State Circuits. SC-22, 5, p. 727-732 6 p.研究成果: Article
Static random access storage
Random access storage
Polysilicon
Aluminum
Data storage equipment
1
引用
(Scopus)
SUBMICROMETER-GATE MOSFET'S BY THE USE OF FOCUSED-ION-BEAM EXPOSURE AND A DRY DEVELOPMENT TECHNIQUE.
Morimoto, H., Tsukamoto, K., Shinohara, H., Inuishi, M. & Kato, T., 1987 2, ： : IEEE Transactions on Electron Devices. ED-34, 2, p. 230-240 11 p.研究成果: Article
GARP Atlantic Tropical Experiment
Focused ion beams
field effect transistors
Ion beam lithography
ion beams
1986
10
引用
(Scopus)
25-ns 256K ×1/64K × 4 CMOS SRAM's
Kayano, S., Ichinose, K., Kohno, Y., Shinohara, H., Anami, K., Murakami, S., Wada, T., Kawai, Y. & Akasaka, Y., 1986, ： : IEEE Journal of Solid-State Circuits. 21, 5, p. 686-691 6 p.研究成果: Article
Random access storage
Detector circuits
Metals
Polysilicon
Feedback
1985
4
引用
(Scopus)
45-NS 256K CMOS STATIC RAM WITH A TRI-LEVEL WORD LINE.
Shinohara, H., Anami, K., Ichinose, K., Wada, T., Kohno, Y., Kawai, Y., Akasaka, Y. & Kayano, S., 1985 10, ： : IEEE Journal of Solid-State Circuits. SC-20, 5研究成果: Article
Random access storage
Networks (circuits)
Polysilicon
Energy dissipation
Data storage equipment
2
引用
(Scopus)
A 45-ns 256K CMOS Static RAM with a Tri-Level Word Line
Shinohara, H., Anami, K., Ichinose, K., Wada, T., Kohno, Y., Kawai, Y., Akasaka, Y. & Kayano, S., 1985, ： : IEEE Journal of Solid-State Circuits. 20, 5, p. 929-934 6 p.研究成果: Article
Random access storage
Networks (circuits)
Polysilicon
Energy dissipation
Data storage equipment
2
引用
(Scopus)
FAST 8K multiplied by 8 MIXED CMOS STATIC RAM.
Shinohara, H., Anami, K., Yoshihara, T., Kihara, Y., Kohno, Y., Akasaka, Y. & Kayano, S., 1985 9, ： : IEEE Transactions on Electron Devices. ED-32, 9, p. 1792-1796 5 p.研究成果: Article
access time
Random access storage
CMOS
Data storage equipment
cells
1983
ANALYSIS OF PARASITIC RESISTANCE EFFECTS IN MOS LSI.
Anami, K., Yoshimoto, M., Shinohara, H., Tomisawa, O. & Nakano, T., 1983 10, ： : Electronics & communications in Japan. 66, 10, p. 106-113 8 p.研究成果: Article
MOSFET devices
Time delay
Experiments
31
引用
(Scopus)
DESIGN CONSIDERATION OF A STATIC MEMORY CELL.
Anami, K., Yoshimoto, M., Shinohara, H., Hirata, Y. & Nakano, T., 1983 8, ： : IEEE Journal of Solid-State Circuits. SC-18, 4, p. 414-418 5 p.研究成果: Article
Random access storage
Data storage equipment
Resistors
Masks
Transistors
134
引用
(Scopus)
DIVIDED WORD-LINE STRUCTURE IN THE STATIC RAM AND ITS APPLICATION TO A 64K FULL CMOS RAM.
Yoshimoto, M., Anami, K., Shinohara, H., Yoshihara, T., Takagi, H., Nagao, S., Kayano, S. & Nakano, T., 1983 10, ： : IEEE Journal of Solid-State Circuits. SC-18, 5, p. 479-485 7 p.研究成果: Article
Random access storage
Polysilicon
Transistors
1982
1
引用
(Scopus)
35 NS 16K NMOS STATIC RAM.
Anami, K., Yoshimoto, M., Shinohara, H., Hirata, Y., Harada, H. & Nakano, T., 1982 10, ： : IEEE Journal of Solid-State Circuits. SC-17, 5, p. 815-820 6 p.研究成果: Article
Random access storage
Alpha particles
Time delay
Energy dissipation
Transistors