Hironori Kasahara – 研究成果 — 早稲田大学

Scopus著者プロファイル

ウェブサイトhttps://w-rdb.waseda.jp/html/100000242_ja.html

h-index

年別の研究成果

Pureに変更を加えた場合、すぐここに表示されます。

59 Conference contribution
33 Article
11 Paper
6 Editorial
その他

100 - 115 / 115 件

Article
Local memory mapping of multicore processors on an automatic parallelizing compiler
Oki, Y., Abe, Y., Yamamoto, K., Yamamoto, K., Shirakawa, T., Yoshida, A., Kimura, K. & Kasahara, H., 2020 3月 1, In: IEICE Transactions on Electronics. E103.C, 3, p. 98-109 12 p.
研究成果: Article › 査読
Multigrain parallel processing on compiler cooperative OSCAR chip multiprocessor architecture
Kimura, K., Kodaka, T., Obata, M. & Kasahara, H., 2003 4月, In: IEICE Transactions on Electronics. E86-C, 4, p. 570-579 10 p.
研究成果: Article › 査読
3 被引用数 (Scopus)
Parallel Processing of Robot-Arm Control Computation on a Multimicroprocessor System
Kasahara, H. & Narita, S., 1985 6月, In: IEEE Journal on Robotics and Automation. 1, 2, p. 104-113 10 p.
研究成果: Article › 査読
106 被引用数 (Scopus)
Parallel processing of robot arm dynamic control computation on multimicroprocessors
Kasahara, H., 1990, In: Microprocessors and Microsystems. 14, 1, p. 3-9 7 p.
研究成果: Article › 査読
3 被引用数 (Scopus)
Parallel Processing of Robot Dynamics Simulation Using Optimal Multiprocessor Scheduling Algorithms
Kasahara, H., Iwata, M., Narita, S. & Fujii, H., 1988, In: Systems and Computers in Japan. 19, 10, p. 45-54 10 p.
研究成果: Article › 査読
Parallel processing of the solution of ordinary differential equations on a general purpose multiprocessor system OSCAR
Kasahara, H., Takane, E., Sato, H., Hisanaga, Y. & Narita, S., 1988 9月 1, In: Bulletin of Centre for Informatics (Waseda University). 8, p. 1-8 8 p.
研究成果: Article › 査読
PARALLEL PROCESSING SCHEME FOR THE CALCULATION OF OPTICAL FLOW AND THE DETERMINATION OF CAMERA MOTION PARAMETERS.
Ito, T., Nakano, K., Kasahara, H. & Narita, S., 1987 3月 1, In: Bulletin of Centre for Informatics (Waseda University). 5, p. 47-59 13 p.
研究成果: Article › 査読
Parallel processing scheme of a basic block in a fortran program on oscar
Honda, H., Kasahara, H. & Narita, S., 1991 1月 1, In: Systems and Computers in Japan. 22, 11, p. 1-13 13 p.
研究成果: Article › 査読
Power-aware compiler controllable chip multiprocessor
Shikano, H., Shirako, J., Wada, Y., Kimura, K. & Kasahara, H., 2008 4月, In: IEICE Transactions on Electronics. E91-C, 4, p. 432-439 8 p.
研究成果: Article › 査読
1 被引用数 (Scopus)
Practical multiprocessor scheduling algorithms for efficient parallel processing
Kasahara, H. & Narita, S., 1985, In: Systems and Computers in Japan. 16, 2, p. 11-19 9 p.
研究成果: Article › 査読
3 被引用数 (Scopus)
Practical Multiprocessor Scheduling Algorithms for Efficient Parallel Processing
Kasahara, H. & Narita, S., 1984 11月, In: IEEE Transactions on Computers. C-33, 11, p. 1023-1029 7 p.
研究成果: Article › 査読
312 被引用数 (Scopus)
Static Coarse Grain Task Scheduling with Cache Optimization Using OpenMP
Nakano, H., Ishizaka, K., Obata, M., Kimura, K. & Kasahara, H., 2003 6月, In: International Journal of Parallel Programming. 31, 3, p. 211-223 13 p.
研究成果: Article › 査読
2 被引用数 (Scopus)
Task Scheduling Algorithms for Multiprocessor Realtime Control Systems.
Kai, M., Kasahara, H., Narita, S. & Ukaji, H., 1986, In: IEEJ Transactions on Electronics, Information and Systems. 106, 12, p. 257-264 8 p.
研究成果: Article › 査読
Task scheduling algorithms for multiprocessor real‐time control systems
Kai, M., Kasahara, H., Narita, S. & Ukaji, H., 1987, In: Electrical Engineering in Japan. 107, 2, p. 120-130 11 p.
研究成果: Article › 査読
What Will 2022 Look Like? The IEEE CS 2022 Report
Alkhatib, H., Faraboschi, P., Frachtenberg, E., Kasahara, H., Lange, D., Laplante, P., Merchant, A., Milojicic, D. & Schwan, K., 2015 3月 1, Computer, 48, 3, p. 68-76 9 p.
研究成果: Article
16 被引用数 (Scopus)