• 966 引用
  • 13 h指数
1981 …2020

年単位の研究成果

Pureに変更を加えた場合、すぐここに表示されます。

研究成果

フィルター
Article
2020

Compiler software coherent control for embedded high performance multicore

Adhi, B. A., Kashimata, T., Takahashi, K., Kimura, K. & Kasahara, H., 2020 3 1, : : IEICE Transactions on Electronics. E103.C, 3, p. 85-97 13 p.

研究成果: Article

Local memory mapping of multicore processors on an automatic parallelizing compiler

Oki, Y., Abe, Y., Yamamoto, K., Yamamoto, K., Shirakawa, T., Yoshida, A., Kimura, K. & Kasahara, H., 2020 3 1, : : IEICE Transactions on Electronics. E103.C, 3, p. 98-109 12 p.

研究成果: Article

2017

IEEE Division VIII Delegate/Director Candidates

Kasahara, H., 2017 1 1, Computer, 50, 8, p. 94-95 2 p.

研究成果: Article

公開

IEEE President-Elect Candidates Address Computer Society Concerns

Kasahara, H., 2017 1 1, Computer, 50, 8, p. 96-100 5 p.

研究成果: Article

公開
2016

Kasahara Voted 2017 Computer Society President-Elect

Kasahara, H. & Gaudiot, J. L., 2016 12 1, Computer, 49, 12, p. 90-92 3 p.

研究成果: Article

2015

What Will 2022 Look Like? The IEEE CS 2022 Report

Alkhatib, H., Faraboschi, P., Frachtenberg, E., Kasahara, H., Lange, D., Laplante, P., Merchant, A., Milojicic, D. & Schwan, K., 2015 3 1, Computer, 48, 3, p. 68-76 9 p.

研究成果: Article

12 引用 (Scopus)
2011

A 45-nm 37.3 GOPS/W heterogeneous multi-core SOC with 16/32 bit instruction-set general-purpose core

Nishii, O., Yuyama, Y., Ito, M., Kiyoshige, Y., Nitta, Y., Ishikawa, M., Yamada, T., Miyakoshi, J., Wada, Y., Kimura, K., Kasahara, H. & Maejima, H., 2011 4, : : IEICE Transactions on Electronics. E94-C, 4, p. 663-669 7 p.

研究成果: Article

2008

Heterogeneous multi-core architecture that enables 54x AAC-LC stereo encoding

Shikano, H., Ito, M., Onouchi, M., Todaka, T., Tsunoda, T., Kodama, T., Uchiyama, K., Odaka, T., Kamei, T., Nagahama, E., Kusaoke, M., Nitta, Y., Wada, Y., Kimura, K. & Kasahara, H., 2008 1, : : IEEE Journal of Solid-State Circuits. 43, 4, p. 902-908 7 p.

研究成果: Article

15 引用 (Scopus)

Power-aware compiler controllable chip multiprocessor

Shikano, H., Shirako, J., Wada, Y., Kimura, K. & Kasahara, H., 2008 4, : : IEICE Transactions on Electronics. E91-C, 4, p. 432-439 8 p.

研究成果: Article

1 引用 (Scopus)
2004
5 引用 (Scopus)
2003
3 引用 (Scopus)

Static Coarse Grain Task Scheduling with Cache Optimization Using OpenMP

Nakano, H., Ishizaka, K., Obata, M., Kimura, K. & Kasahara, H., 2003 6 1, : : International Journal of Parallel Programming. 31, 3, p. 211-223 13 p.

研究成果: Article

2 引用 (Scopus)
2002
107 引用 (Scopus)

Humanoid robots in Waseda University - Hadaly-2 and WABIAN

Hashimoto, S., Narita, S., Kasahara, H., Shirai, K., Kobayashi, T., Takanishi, A., Sugano, S., Yamaguchi, J., Sawada, H., Takanobu, H., Shibuya, K., Morita, T., Kurata, T., Onoe, N., Ouchi, K., Noguchi, T., Niwa, Y., Nagayama, S., Tabayashi, H., Matsui, I. および43人, Obata, M., Matsuzaki, H., Murasugi, A., Kobaysashi, H., Haruyama, S., Okada, T., Hidaki, Y., Taguchi, Y., Hoashi, K., Morikawa, E., Iwano, Y., Araki, D., Suzuki, J., Yokoyama, M., Dawa, I., Nishino, D., Inoue, S., Hirano, T., Soga, E., Gen, S., Yanada, T., Kato, K., Sakamoto, S., Ishii, Y., Matsuo, S., Yamamoto, Y., Sato, K., Hagiwara, T., Ueda, T., Honda, N., Hashimotoo, D., Hananmoto, T., Kayaba, S., Kojima, T., Iwata, H., Kubodera, H., Matsuki, R., Nakajima, T., Nitto, K., Yamammoto, D., Kamizaki, Y., Nagaike, S. & Kunitake, Y., 2002 1, : : Autonomous Robots. 12, 1, p. 25-38 14 p.

研究成果: Article

33 引用 (Scopus)
1998
10 引用 (Scopus)
1997

Data-localization scheduling inside processor-cluster for multigrain parallel processing

Yoshida, A., Koshizuka, K. N. I., Ogata, W. & Kasahara, H., 1997 1 1, : : IEICE Transactions on Information and Systems. E80-D, 4, p. 473-478 6 p.

研究成果: Article

1992
1 引用 (Scopus)
1991

Coarse grain parallelism detection scheme of a fortran program

Honda, H. & Kasahara, H., 1991, : : Systems and Computers in Japan. 22, 12, p. 24-36 13 p.

研究成果: Article

3 引用 (Scopus)

Parallel processing scheme of a basic block in a fortran program on oscar

Honda, H., Kasahara, H., Kasahara, H. & Narita, S., 1991, : : Systems and Computers in Japan. 22, 11, p. 1-13 13 p.

研究成果: Article

1990
3 引用 (Scopus)
1988

Application of df/ihs to minimum total weighted flow time multiprocessor scheduling problems

Kasahara, H., Kai, M., Narita, S. & Wada, H., 1988 6, : : Systems and Computers in Japan. 19, 6, p. 25-34 10 p.

研究成果: Article

1987

Task scheduling algorithms for multiprocessor real‐time control systems

Kai, M., Kasahara, H., Narita, S. & Ukaji, H., 1987, : : Electrical Engineering in Japan. 107, 2, p. 120-130 11 p.

研究成果: Article

1986
1985
101 引用 (Scopus)
2 引用 (Scopus)
1984
288 引用 (Scopus)