• 8 引用
  • 2 h指数
20182019

年単位の研究成果

Pureに変更を加えた場合、すぐここに表示されます。

フィンガープリント Jinghao Yeが有効な場合、研究トピックを掘り下げます。このトピックラベルは、この人物の業績からのものです。これらはともに一意のフィンガープリントを構成します。

  • 1 同様のプロファイル

研究成果

  • 8 引用
  • 2 h指数
  • 5 Conference contribution

A Bit-Segmented Adder Chain based Symmetric Transpose Two-Block FIR Design for High-Speed Signal Processing

Ye, J., Yanagisawa, M. & Shi, Y., 2019 11, Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption. Institute of Electrical and Electronics Engineers Inc., p. 29-32 4 p. 8953124. (Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption).

研究成果: Conference contribution

  • An adder-segmentation-based FIR for high speed signal processing

    Ye, J., Yanagisawa, M. & Shi, Y., 2019 10, Proceedings - 2019 IEEE 13th International Conference on ASIC, ASICON 2019. Ye, F. & Tang, T-A. (版). IEEE Computer Society, 8983612. (Proceedings of International Conference on ASIC).

    研究成果: Conference contribution

  • 1 引用 (Scopus)

    A Zero-Gating Processing Element Design for Low-Power Deep Convolutional Neural Networks

    Ye, L., Ye, J., Yanagisawa, M. & Shi, Y., 2019 11, Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption. Institute of Electrical and Electronics Engineers Inc., p. 317-320 4 p. 8953157. (Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption).

    研究成果: Conference contribution

  • Static error analysis and optimization of faithfully truncated adders for area-power efficient FIR designs

    Ye, J., Togawa, N., Yanagisawa, M. & Shi, Y., 2019 1 1, 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8702386. (Proceedings - IEEE International Symposium on Circuits and Systems; 巻数 2019-May).

    研究成果: Conference contribution

  • 2 引用 (Scopus)

    A low cost and high speed CSD-based symmetric transpose block FIR implementation

    Ye, J., Shi, Y., Togawa, N. & Yanagisawa, M., 2018 1 8, Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. IEEE Computer Society, 巻 2017-October. p. 311-314 4 p.

    研究成果: Conference contribution

  • 5 引用 (Scopus)