川村 一志

講師(任期付)

  • 14 引用
  • 2 h指数
20132019
Pureに変更を加えた場合、すぐここに表示されます。

研究成果 2013 2019

  • 14 引用
  • 2 h指数
  • 9 Conference contribution
  • 5 Article
2019
公開
Field programmable gate arrays (FPGA)
Networks (circuits)
2018

A loop structure optimization targeting high-level synthesis of fast number theoretic transform

Kawamura, K., Yanagisawa, M. & Togawa, N., 2018 5 9, 2018 19th International Symposium on Quality Electronic Design, ISQED 2018. IEEE Computer Society, 巻 2018-March. p. 106-111 6 p.

研究成果: Conference contribution

Field programmable gate arrays (FPGA)
Cryptography
Program processors
Hardware
High level synthesis

A selector-based FFT processor and its FPGA implementation

Hirai, Y., Kawamura, K., Yanagisawa, M. & Togawa, N., 2018 5 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 88-89 2 p.

研究成果: Conference contribution

Fast Fourier transforms
Field programmable gate arrays (FPGA)
Signal processing
Processing
2017
Extractor
Wire
Evaluation
Networks (circuits)
Partitioning
1 引用 (Scopus)

Rotator-based multiplexer network synthesis for field-data extractors

Ito, K., Kawamura, K., Tamiya, Y., Yanagisawa, M. & Togawa, N., 2017 4 19, Proceedings - 29th IEEE International System on Chip Conference, SOCC 2016. IEEE Computer Society, p. 194-199 6 p. 7905464

研究成果: Conference contribution

Wire
2016
3 引用 (Scopus)

A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration

Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 5 31, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 7482547

研究成果: Conference contribution

clocks
Field programmable gate arrays (FPGA)
Clocks
synthesis
Networks (circuits)

A high-performance circuit design algorithm using data dependent approximation

Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 12 27, ISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things. Institute of Electrical and Electronics Engineers Inc., p. 95-96 2 p. 7799750

研究成果: Conference contribution

Networks (circuits)
approximation
adding circuits
Adders
time measurement
1 引用 (Scopus)
Extractor
Partitioning
Stream Processing
Consecutive
Count
3 引用 (Scopus)

Clock skew estimate modeling for FPGA high-level synthesis and its application

Fujiwara, K., Kawamura, K., Yanagisawa, M. & Togawa, N., 2016 7 19, Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015. Institute of Electrical and Electronics Engineers Inc., 7516905

研究成果: Conference contribution

Field programmable gate arrays (FPGA)
Clocks
High level synthesis
Networks (circuits)
2015
1 引用 (Scopus)

A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs

Fujiwara, K., Abe, S., Kawamura, K., Yanagisawa, M. & Togawa, N., 2015 2 5, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. February 版 Institute of Electrical and Electronics Engineers Inc., 巻 2015-February. p. 244-247 4 p. 7032765

研究成果: Conference contribution

Field programmable gate arrays (FPGA)
Delay circuits
Costs
Scheduling
High level synthesis
2 引用 (Scopus)

A floorplan-aware high-level synthesis technique with delay-variation tolerance

Kawamura, K., Hagio, Y., Shi, Y. & Togawa, N., 2015 9 30, Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015. Institute of Electrical and Electronics Engineers Inc., p. 122-125 4 p. 7285065

研究成果: Conference contribution

Scheduling
Silicon
High level synthesis
2 引用 (Scopus)
High-level Synthesis
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Module
Costs
2013

A partial redundant fault-secure high-level synthesis algorithm for RDR architectures

Kawamura, K., Tanaka, S., Yanagisawa, M. & Togawa, N., 2013, Proceedings - IEEE International Symposium on Circuits and Systems. p. 1736-1739 4 p. 6572200

研究成果: Conference contribution

Scheduling
High level synthesis
1 引用 (Scopus)
High-level Synthesis
Chip
Interconnect
Energy Consumption
Energy utilization