小林 学

研究成果

年別の研究成果 1999 2014 2022 2022

• 30 Conference contribution
• 17 Article
• 2 Conference article
• 1 Chapter
• 1 その他
  • 1 Editorial

年別の研究成果

年別の研究成果

検索結果

• Article

  Adaptive decoding algorithms for low-density parity-check codes over the binary erasure channel

  Hosoya, G., Yagi, H., Kobayashi, M. & Hirasawa, S., 2009 10月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E92-A, 10, p. 2418-2430 13 p.

  研究成果: Article › 査読

  • Low-density Parity-check (LDPC) Codes 100%
  • Decoding 75%
  • Binary 51%
  • Belief Propagation 43%
  • Terminate 8%
  2 被引用数 (Scopus)

• An efficient heuristic search method for maximum likelihood decoding of linear block codes using dual codes

  Okada, T., Kobayashi, M. & Hirasawa, S., 2002 2月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 2, p. 485-489 5 p.

  研究成果: Article › 査読

  • Heuristic Search 100%
  • Dual Codes 97%
  • Block Codes 93%
  • Heuristic Method 90%
  • Search Methods 87%
  5 被引用数 (Scopus)

• A new latent class model for analysis of purchasing and browsing histories on EC sites

  Goto, M., Mikawa, K., Hirasawa, S., Kobayashi, M., Suko, T. & Horii, S., 2015 12月 1, In: Industrial Engineering and Management Systems. 14, 4, p. 335-346 12 p.

  研究成果: Article › 査読

  Open Access

  • Latent Class Model 100%
  • European Community 69%
  • customer 63%
  • Purchasing 56%
  • purchase 44%
  9 被引用数 (Scopus)

• An improved method of reliability-based maximum likelihood decoding algorithms using an order relation among binary vectors

  Yagi, H., Kobayashi, M., Matsushima, T. & Hirasawa, S., 2004 10月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 10, p. 2493-2502 10 p.

  研究成果: Article › 査読

  • Order Relation 100%
  • Decoding 92%
  • Maximum likelihood 79%
  • Maximum Likelihood 74%
  • Binary 63%

• A study of learning a sparse metric matrix using l₁ regularization based on supervised learning

  Mikawa, K., Kobayashi, M. & Goto, M., 2015, In: Journal of Japan Industrial Management Association. 66, 3, p. 230-239 10 p.

  研究成果: Article › 査読

  • Supervised Learning 100%
  • Regularization 91%
  • Supervised learning 74%
  • Learning 63%
  • Matrix 62%

• Circuit design of 2-input reconfigurable dynamic logic based on double gate MOSFETs with whole set of 16 functions

  Kato, J., Watanabe, S., Ninomiya, H., Kobayashi, M. & Miura, Y., 2014, In: Contemporary Engineering Sciences. 7, 1-4, p. 87-102 16 p.

  研究成果: Article › 査読

  • logic 100%
  • Voltage 64%
  • Set theory 57%
  • Networks (circuits) 49%
  • government supervision 35%
  1 被引用数 (Scopus)

• Circuit design of reconfigurable dynamic logic based on double gate cntfets focusing on number of states of back gate voltages

  Kato, J., Watanabe, S., Ninomiya, H., Kobayashi, M. & Miura, Y., 2014, In: Contemporary Engineering Sciences. 7, 1-4, p. 39-52 14 p.

  研究成果: Article › 査読

  • logic 100%
  • Back 89%
  • Voltage 64%
  • Networks (circuits) 49%
  • Electric potential 46%
  2 被引用数 (Scopus)

• Circuit design of reconfigurable logic based on double-gate CNTFETs

  Kobayashi, M., Ninomiya, H. & Watanabe, S., 2013 7月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 7, p. 1642-1644 3 p.

  研究成果: Article › 査読

  • Circuit Design 100%
  • Dynamic Logic 76%
  • Logic circuits 62%
  • Logic 52%
  • XNOR 44%
  3 被引用数 (Scopus)

• Complexity Reduction of the Gazelle and Snyders Decoding Algorithm for Maximum Likelihood Decoding

  Yagi, H., Kobayashi, M. & Hirasawa, S., 2003 10月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E86-A, 10, p. 2461-2472 12 p.

  研究成果: Article › 査読

  • Decoding 100%
  • Maximum likelihood 85%
  • Maximum Likelihood 80%
  • Likely 53%
  • Search Algorithm 41%
  5 被引用数 (Scopus)

• Density evolution analysis of robustness for LDPC codes over the Gilbert-Elliott channel

  Kobayashi, M., Yagi, H., Matsushima, T. & Hirasawa, S., 2008 10月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E91-A, 10, p. 2754-2764 11 p.

  研究成果: Article › 査読

  • Low-density Parity-check (LDPC) Codes 100%
  • Decoding 58%
  • Robustness 57%
  • Error Probability 25%
  • Parity 23%

• On decoding methods beyond the BCH bound and their applications to soft-decision decoding

  Kobayashi, M., Matsushima, T. & Hirasawa, S., 1999 9月 1, In: Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi). 82, 9, p. 39-51 13 p.

  研究成果: Article › 査読

  • Decoding 100%

• Privacy-preserving distributed calculation methods of a least-squares estimator for linear regression models

  Suko, T., Horii, S., Kobayashi, M., Goto, M., Matsushima, T. & Hirasawa, S., 2014, In: Journal of Japan Industrial Management Association. 65, 2, p. 78-88 11 p.

  研究成果: Article › 査読

  • Privacy Preserving 100%
  • Calculation Method 82%
  • Least Squares Estimator 79%
  • Linear Regression Model 72%
  • Linear regression 64%
  1 被引用数 (Scopus)

• Probabilistic fault diagnosis and its analysis in multicomputer systems

  Kobayashi, M., Matsushima, T. & Hirasawa, S., 2018 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E101A, 12, p. 2072-2081 10 p.

  研究成果: Article › 査読

  • Multicomputers 100%
  • Fault Diagnosis 97%
  • Failure analysis 53%
  • Unit 43%
  • Error Probability 17%

• Reconfigurable circuit design based on arithmetic logic unit using double-gate cntfets

  Ninomiya, H., Kobayashi, M., Miura, Y. & Watanabe, S., 2014, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E97-A, 2, p. 675-678 4 p.

  研究成果: Article › 査読

  • Circuit Design 100%
  • Carbon nanotube field effect transistors 98%
  • Field-effect Transistor 77%
  • Logic 52%
  • Unit 45%

• Reconfigurable dynamic logic circuit generating t-term Boolean functions based on double-gate CNTFETs

  Kobayashi, M., Ninomiya, H., Miura, Y. & Watanabe, S., 2014 5月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E97-A, 5, p. 1051-1058 8 p.

  研究成果: Article › 査読

  • Dynamic Logic 100%
  • Boolean functions 89%
  • Logic circuits 82%
  • Boolean Functions 70%
  • Term 38%

• Reduced reconfigurable logic circuit design based on double gate CNTFETs using ambipolar binary decision diagram

  Ninomiya, H., Kobayashi, M. & Watanabe, S., 2013 1月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 1, p. 356-359 4 p.

  研究成果: Article › 査読

  • Field-effect Transistor 100%
  • Logic Design 92%
  • Circuit Design 85%
  • Binary Decision Diagram 85%
  • Carbon nanotube field effect transistors 84%
  7 被引用数 (Scopus)

• The construction of periodically time-variant convolutional codes using binary linear block codes

  Ogasahara, N., Kobayashi, M. & Hirasawa, S., 2007 9月 1, In: Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi). 90, 9, p. 31-40 10 p.

  研究成果: Article › 査読

  • Convolutional codes 100%
  • Block codes 94%
  2 被引用数 (Scopus)